Step-Shaped Edge Termination for High-Voltage Semiconductor Devices
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Solution Overview
Problem
High-voltage semiconductor devices require effective edge termination solutions to manage electric field strength at the die edges, as existing methods like planar and mesa edge terminations are either space-intensive or unsuitable for mass production.
Innovation Solution
A semiconductor device design featuring a step in the edge termination with a channel stopper at the bottom of a trench, incorporating doping zones of varying conductivity types to form pn-junctions and an insulating material, which reduces the lateral space required for edge termination while effectively diverting electrical potential lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar edge termination with field plates is used, then electric field strength is reduced, but lateral space required increases significantly
Solution Approach 1:
The patent transitions from planar (2D) edge termination to a three-dimensional stepped structure. The edge termination zone includes multiple levels at different heights, allowing electric field control to occur in the vertical dimension rather than requiring excessive lateral space. This dimensional change enables compact design while maintaining field strength management.
Solution Approach 2:
The edge termination zone is divided into multiple discrete steps or levels rather than being a continuous planar structure. Each step can be independently doped and configured to manage electric field distribution at different locations, providing modular control over field strength while reducing overall lateral footprint.
2Area of stationary object
If mesa edge termination with trenches is used, then lateral space is reduced, but manufacturing complexity increases due to raw processing techniques
Solution Approach 1:
The patent replaces mechanical/raw processing techniques (laser processing, lapping, grinding, sand blasting) with standard semiconductor manufacturing processes. The stepped structure is formed using conventional photolithography, etching, and doping techniques that are already established in wafer fabrication, eliminating the need for specialized post-processing equipment and methods.
Solution Approach 2:
The patent achieves the desired stepped geometry through controlled changes in doping parameters and etch conditions during standard fabrication processes. By adjusting doping concentrations, implantation angles, and etch selectivities, the multi-level structure is created using routine semiconductor manufacturing parameters rather than requiring mechanical intervention.
3Ease of manufacture
If standard doping techniques are used in stepped structures, then manufacturing is simplified, but precision in doping zone formation decreases
Solution Approach 1:
The patent applies different doping conditions to different regions of the stepped structure. Each step or level can receive tailored doping treatment with specific concentrations, types, and depths appropriate for its local electric field requirements. This localized approach maintains high precision while using standard doping equipment and techniques.
Solution Approach 2:
The patent performs preliminary masking and positioning steps before doping to ensure precise dopant placement in the stepped structure. Photolithographic patterns are formed in advance to define exact doping zones, and spacer layers are deposited beforehand to control doping depths. These preparatory actions enable accurate doping zone formation using conventional doping processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces the space needed for edge termination, enhances blocking voltage capabilities, and is compatible with thin wafer technologies, maintaining mechanical stability and robustness against processing residues.
Implementation Method 1
A first doping zone of a second conductivity type is formed in the semiconductor body along the lateral surface of the step and forms a pn-junction with the drift region
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a semiconductor substrate having first and second sides, laterally spaced semiconductor devices integrated into the semiconductor substrate, and a drift region of a first conductivity type. Trenches are formed in the semiconductor substrate at the first side of the semiconductor substrate between laterally adjacent semiconductor devices, each of the trenches having two sidewalls and a bottom. First doping zones of a second conductivity type are formed in the semiconductor substrate at least along the sidewalls of the trenches. The first doping zones form pn-junctions with the drift region. Second doping zones of the first conductivity type are formed in the semiconductor substrate at least along a part of the bottom of the trenches. The second doping zones adjoin the drift region. The semiconductor substrate is cut along the second doping zones in the trenches to separate the semiconductor devices.