Step-Shaped Floating Gate for Flash Memory Coupling Ratio

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Solution Overview

Problem

Flash memory devices face challenges in power consumption and data retention/erase performance, as existing structures do not efficiently optimize the coupling ratio between the floating gate and control gate, leading to suboptimal programming voltage and uniformity of the inter-gate dielectric layer.

Innovation Solution

The implementation of non-vertical step-shaped floating gate structures with varying outer sidewall thicknesses, which enhance the coupling ratio by increasing the top surface area and improving the capacitance between the floating gate and control gate, allowing for reduced programming voltage while maintaining performance and enabling different retention and erase capabilities on the same chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional floating gate structures are used, then manufacturing is simpler, but coupling ratio between floating gate and control gate is insufficient

Engineering Contradiction:

Improvecoupling ratioVSAvoidfloating gate structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The floating gate structure transitions from a conventional planar configuration to a three-dimensional stepped configuration with multiple levels. This dimensional change increases the effective surface area of the floating gate that interfaces with the control gate, thereby enhancing the coupling ratio without simply scaling up the lateral dimensions

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The floating gate is divided into multiple stepped levels or terraces, creating a segmented structure. Each step provides an additional interface area with the control gate, and the segmentation allows for optimized electrical field distribution across different regions of the gate structure

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If conventional floating gate structures are used, then programming voltage requirements are standard, but power consumption is higher

Engineering Contradiction:

Improvepower consumptionVSAvoidprogramming efficiency

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The stepped floating gate structure enables more efficient charge storage and retrieval mechanisms, allowing for reduced programming voltages and shorter programming pulses. This effectively makes the programming operation less energy-intensive, consuming power only when needed for data programming rather than continuous power requirements

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Manufacturing precision

If conventional floating gate structures are used, then uniformity of inter-gate dielectric layer is difficult to achieve, but manufacturing process is simpler

Engineering Contradiction:

Improveuniformity of inter-gate dielectric layerVSAvoidfloating gate structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The stepped floating gate structure is formed with predetermined geometry and surface characteristics before the inter-gate dielectric layer deposition. This preliminary structuring creates a more uniform substrate surface that facilitates consistent dielectric layer formation, improving uniformity of the inter-gate dielectric across the device area

Inventive Principle:

Principle #10Preliminary action

4Reliability

If floating gate top surface area is increased, then coupling ratio is enhanced, but device area increases

Engineering Contradiction:

Improvecoupling ratioVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of increasing the lateral footprint of the floating gate, the structure utilizes vertical dimensionality with stepped levels. This allows the floating gate to achieve greater effective surface area for coupling with the control gate while maintaining a compact lateral footprint, thus improving coupling ratio without proportionally increasing the overall device area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The non-vertical step-shaped floating gate structures reduce power consumption, enhance data retention and erase performance, and improve the uniformity and conformality of the inter-gate dielectric layer, achieving improved coupling ratios and varied performance characteristics on the same chip.

Implementation Method 1

enhance the coupling ratio by increasing the top surface area and improving the capacitance between the floating gate and control gate

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11018233B2Flash memory cell structure with step-shaped floating gate

Publication Date: 2021.05.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.