Step Gate Dielectric Structure for LDMOS
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Solution Overview
Problem
Conventional LDMOS devices face challenges in reducing on-resistance (RDSon) while maintaining high breakdown voltage, leading to high power consumption and reliability issues due to increased device size.
Innovation Solution
A semiconductor device with a step gate dielectric structure is formed using a hard mask layer and additional deposition and photolithography/etching processes, which reduces the current path from the source to the drain, thereby lowering on-resistance while maintaining high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the device size is increased to withstand high off-state breakdown voltage, then the breakdown voltage is improved, but the on-resistance cannot be reduced
Solution Approach 1:
The gate dielectric layer is segmented into multiple layers with different etch rates, creating a stepped structure that allows different regions to have different effective dielectric thicknesses. This segmentation enables the device to achieve both high breakdown voltage and low on-resistance by having thicker dielectric in high-voltage regions and thinner dielectric in low-voltage regions.
Solution Approach 2:
Different portions of the gate dielectric structure have different local properties - specifically, different etch rates and resulting thicknesses. The first dielectric material has a different etch rate than the second dielectric material, creating local variations in dielectric thickness that optimize performance for different voltage requirements in different device regions.
2Strength
If the device size is increased to withstand high off-state breakdown voltage, then the breakdown voltage is improved, but power consumption increases due to higher on-resistance
Solution Approach 1:
The gate dielectric is divided into multiple layers with different etch rates, creating a stepped structure that reduces the current path length in low-voltage regions. This segmentation allows the device to maintain high breakdown voltage capability while reducing on-resistance and consequently power consumption in regions where full breakdown voltage is not required.
Solution Approach 2:
The etch rate parameter is changed between different dielectric materials to create the stepped structure. By selecting materials with different etch rates, the invention achieves varying dielectric thicknesses that optimize the balance between breakdown voltage and on-resistance, thereby reducing power consumption.
3Manufacturing precision
If additional deposition and photolithography/etching processes are used to form the step gate dielectric structure, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
Multiple dielectric layers are deposited and patterned in advance before the final gate structure formation. The first and second dielectric materials are deposited and patterned sequentially, creating the stepped structure beforehand. This preliminary action allows for precise control of the gate dielectric thickness profile while integrating smoothly into the overall fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The step gate dielectric structure effectively reduces on-resistance (RDSon) and power consumption while maintaining high breakdown voltage, improving the reliability and efficiency of the semiconductor device.
Implementation Method 1
An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material to the etchant
Data Source
AI summary
A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. A method for forming a semiconductor device is also disclosed.