Step-Increasing Threshold Voltage Memory Access Method
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Solution Overview
Problem
Conventional memory accessing methods waste time and increase power consumption by requiring multiple word line enablements to correctly determine data stored in multi-bit and multi-level cell memory cells.
Innovation Solution
A method that redefines threshold voltages and uses a step-increasing threshold voltage operation to write and read data, allowing data to be stored and retrieved with fewer word line enablements, specifically by defining 2n levels for n-bit storage and boosting threshold voltages in a controlled manner to reduce the number of enablements required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory accessing method is used with multiple word line enablements, then data can be correctly determined in multi-level cell memory, but memory accessing time increases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-boosting threshold voltages of memory cells to higher levels before data reading. Specifically, threshold voltages are boosted from level 0 to level 1, then from level 1 to level 2, and finally from level 2 to level 3 in advance. This preliminary voltage adjustment enables the memory cell to be read correctly with fewer subsequent word line enablements, thereby reducing access time while maintaining data determination accuracy.
Solution Approach 2:
The patent changes the threshold voltage parameter of memory cells dynamically during the reading process. By sequentially boosting the threshold voltage from level 0 to level 1, then to level 2, and finally to level 3, the system adapts the voltage parameter to match the stored data levels. This parameter change allows for reduced word line enablements and shorter access times while maintaining accurate data reading.
2Measurement precision
If conventional memory accessing method is used with multiple word line enablements, then data can be correctly determined in multi-level cell memory, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-boosting threshold voltages of memory cells to higher levels before data reading. Specifically, threshold voltages are boosted from level 0 to level 1, then from level 1 to level 2, and finally from level 2 to level 3 in advance. This preliminary voltage adjustment enables the memory cell to be read correctly with fewer subsequent word line enablements, thereby reducing access time while maintaining data determination accuracy.
Solution Approach 2:
The patent changes the threshold voltage parameter of memory cells dynamically during the reading process. By sequentially boosting the threshold voltage from level 0 to level 1, then to level 2, and finally to level 3, the system adapts the voltage parameter to match the stored data levels. This parameter change allows for reduced word line enablements and shorter access times while maintaining accurate data reading.
3Loss of time
If threshold voltages are boosted step-increasingly from level 0 to level 3, then word line enablements are reduced, but the operation complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the threshold voltage boosting process into distinct sequential steps: first from level 0 to level 1, then from level 1 to level 2, and finally from level 2 to level 3. Each step corresponds to reading a specific bit position (first bit, second bit, third bit respectively). This segmentation makes the complex operation more manageable and implementable while achieving reduced word line enablements and shorter access times.
Data Source
AI summary
A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2ā1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2nā1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.