Step Interconnect Metallization for Panel Level Packaging
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Solution Overview
Problem
Current semiconductor die packaging methods induce build-up stresses due to epoxy and solder usage, leading to failures such as solder joint fatigue and nitride passivation/die cracking, and require costly materials like leadframes and die attach compounds.
Innovation Solution
A method involving a substrate with a thermal release tape and photoresist layer for direct metallization of semiconductor dies, eliminating the need for epoxy and leadframes, with 3D metallization forming step interconnects through die sidewalls and using photoresist as a buffer to reduce stress and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If traditional epoxy and solder are used for die attachment, then mechanical bonding is achieved, but build-up stress is induced causing solder joint fatigue and die cracking
Solution Approach 1:
The patent removes epoxy and solder materials from the die attachment process entirely. Instead, it uses direct metal-to-semiconductor bonding through metallization layers formed by electroplating, extracting the harmful intermediary materials that cause stress buildup while maintaining mechanical bonding functionality.
Solution Approach 2:
The patent introduces a metallization layer as an intermediary between the die and substrate. This metal layer serves as the bonding interface, replacing epoxy and solder, and enables direct electrical and mechanical connection without the stress-induced failures associated with traditional organic or solder-based intermediaries.
2Ease of manufacture
If leadframe carrier and die attach epoxy are used, then die mounting is achieved, but packaging cost increases
Solution Approach 1:
The patent extracts and eliminates leadframe carriers and die attach epoxy from the packaging process. It achieves die mounting through direct bonding of metallization layers on the die to the substrate, removing the need for expensive traditional packaging materials and simplifying the overall structure.
Solution Approach 2:
The patent replaces expensive, complex packaging materials (leadframes, epoxy) with simpler, more cost-effective metallization layers that can be directly formed on the die and substrate through electroplating processes, reducing material costs while maintaining functionality.
3Reliability
If through holes are drilled and electroplated to form closed-loop circuits, then interconnect is achieved, but process complexity increases
Solution Approach 1:
The patent extracts the complex process of drilling through-holes and forming closed-loop circuits. Instead, it uses direct metallization deposition through shadow masks to create interconnect pathways, eliminating the need for mechanical drilling and complex via formation steps.
Solution Approach 2:
The patent replaces mechanical drilling and complex electroplating processes with a shadow mask-based metallization deposition system. This substitution simplifies the interconnect formation process by using photomask alignment and direct metal deposition rather than mechanical hole drilling and multi-step plating.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces stress on semiconductor dies, lowers packaging costs by eliminating epoxy and leadframe materials, and enables large-area processing, resulting in a more reliable and cost-effective packaging solution.
Implementation Method 1
the substrate along with the thermal release tape is removed so as to reveal said metallization layer adjacent to the semiconductor die
Implementation Method 2
application of a photoresist layer on both the semiconductor die and the thermal release tape
Implementation Method 3
a metallization layer is formed such that the metallization layer contacts said exposed semiconductor die
Data Source
AI summary
This disclosure relates to a new package concept that eliminates the need for epoxy or epoxy solder used in traditional clip/lead frame-based power packages. The disclosure overcomes this disadvantage in clip-based packages by depositing the interconnect structure directly to the bod pads. The formation of the interconnect done at lower temperature leads to lower stress induced onto the die. Another advantage of the present disclosure is that semiconductor dies packaged using a method according to the present disclosure will have smaller footprint as the pads are directly built up/deposited. Another advantage of the method according to the present disclosure is that it allows large scale, i.e., panel level processing. Such a panel may include multiple ICs, or transistor or any other semiconductor devices.