Step Topography Passivation Stack for High-Voltage Edge Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High voltage semiconductor devices face challenges in maintaining impermeability and stability, particularly at step topographies, due to moisture-induced corrosion and ion transport, which can lead to device failure.
Innovation Solution
A layer stack comprising an electrically insulating buffer layer, a SiC layer, and a silicon nitride layer or a nitrided SiC surface region is applied over the step topography to enhance impermeability and stability, effectively shielding the device from environmental impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick passivation layer is used to cover and protect underlying structures, then protection against moisture corrosion is improved, but vulnerability at step topography edges increases leading to device failure
Solution Approach 1:
The passivation structure is divided into multiple functional layers: a first passivation layer (e.g., silicon nitride) providing primary moisture barrier, a dielectric layer filling the trench to protect step edges, and a second passivation layer providing additional protection. This segmentation allows each layer to address specific vulnerability points, particularly protecting the edges of step topographies where corrosion is most likely to initiate.
Solution Approach 2:
A dielectric layer is introduced as an intermediary material filling the trench formed at the step topography. This intermediate layer physically protects the vulnerable edge regions from moisture exposure and prevents direct contact between the passivation layer and corrosive environments at the step edges, thereby eliminating the vulnerability without compromising the overall protective function.
2Reliability
If a thick passivation layer is applied to ensure impermeability, then stability against ion transport is improved, but device complexity increases
Solution Approach 1:
The passivation system is segmented into multiple layers with distinct functions: the first passivation layer provides the primary impermeability barrier against ion transport, while the dielectric layer and second passivation layer provide supplementary protection and structural support. This segmentation achieves high reliability without requiring an excessively thick single layer, thereby balancing impermeability requirements with device complexity constraints.
Solution Approach 2:
The passivation structure employs composite material architecture combining different dielectric materials (e.g., silicon nitride, silicon oxide, or other low-k dielectrics) with complementary properties. This composite approach provides enhanced impermeability and stability against ion transport while maintaining reasonable structural complexity, as each material contributes specific protective characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a high degree of impermeability and stability, ensuring effective passivation of step topographies and preventing device failure by fully covering vertical sidewalls and edges, thus maintaining reliable operation under high voltage conditions.
Implementation Method 1
A layer stack covers the step topography. The layer stack includes an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer
Data Source
AI summary
A high voltage semiconductor device includes a semiconductor substrate including an upper surface, a high voltage electrically conductive structure disposed on the semiconductor substrate, a first step topography at an edge of the high voltage electrically conductive structure, a varying lateral doping zone disposed within the semiconductor substrate, and a layer stack including an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer, and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer, wherein the layer stack conforms to the first step topography and extends over the varying lateral doping zone.