Multi-Floor Step Pattern Structure Formation via Sacrificial Layer Etching
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Solution Overview
Problem
The existing methods for forming step pattern structures in vertical-type semiconductor devices require multiple photolithography and etching processes, increasing processing costs and complexity.
Innovation Solution
A method involving the alternate stacking of insulating interlayers and sacrificial layers, with a passivation layer formed using SiCl4 and O2 gas, allows for the reduction of photolithography steps by maintaining the thickness and shape of the photoresist pattern during trimming processes, enabling the formation of a multi-floor step pattern structure within a single etching chamber.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography and etching processes are used to form a step pattern structure, then the structure can be formed with precise control, but the processing cost and process complexity increase
Solution Approach 1:
The patent combines multiple photolithography and etching processes into a single integrated process. Specifically, it forms a stacked structure of insulating interlayers and sacrificial layers, then uses one photolithography process to create a photoresist pattern that serves as a mask for subsequent etching, eliminating the need for separate photolithography steps for each layer modification.
Solution Approach 2:
The patent performs preliminary stacking of insulating interlayers and sacrificial layers before the photolithography process. This preliminary structure preparation allows the single photolithography step to control the formation of multiple stepped patterns simultaneously, rather than requiring sequential patterning of each layer.
2Manufacturing precision
If multiple photolithography processes are used to form a step pattern structure, then each layer can be precisely patterned, but the number of processing steps and cost increase
Solution Approach 1:
The patent merges multiple photolithography processes into one by creating a stacked structure where insulating interlayers and sacrificial layers are alternately deposited, then using a single photoresist pattern to control etching of multiple layers simultaneously, achieving multi-layer patterning in one photolithography step.
Solution Approach 2:
The photoresist pattern formed in the single photolithography process serves multiple functions: it acts as an etching mask for the sacrificial layers, defines the stepped pattern geometry, and controls the exposure of insulating interlayers. This multi-functional use of one photolithography process eliminates the need for multiple separate patterning steps.
3Device complexity
If traditional multi-step photolithography is used, then complex step patterns can be formed, but processing time and cost increase
Solution Approach 1:
The patent performs preliminary stacking of alternating insulating interlayers and sacrificial layers before photolithography. This pre-formed stacked structure enables a single photolithography process to define complex multi-level stepped patterns that would otherwise require multiple sequential patterning operations, significantly reducing processing time.
Solution Approach 2:
The patent transitions from planar sequential patterning to three-dimensional simultaneous patterning by stacking layers vertically. The single photolithography process patterns multiple horizontal layers at different heights, utilizing the vertical dimension to achieve complex stepped patterns in one operation rather than multiple sequential steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the number of photolithography steps, thereby reducing processing costs and simplifying the formation of a vertical-type semiconductor device with a low-cost, high-integration step pattern structure.
Implementation Method 1
A first passivation layer may be formed by using SiCl4 and an O2 gas as reaction gases
Implementation Method 2
A first preliminary step pattern structure is formed by etching portions of one uppermost insulating interlayer and one uppermost sacrificial layer using the first photoresist pattern as an etching mask
Data Source
AI summary
A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.