Step Seal Ring Layout for Thermal-Mismatch Corner Bonding

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Solution Overview

Problem

The integration of multiple device dies in a semiconductor package, such as System on Integrate Chip (SoIC), often results in cracking and non-bonding issues at the corners due to thermal expansion mismatch between different materials, particularly at the interface of seal rings.

Innovation Solution

The implementation of a stepped seal ring structure, where the outer seal ring lacks an upper portion or has a narrower upper portion than the inner seal ring, made of materials with different thermal expansion coefficients, reduces stress and prevents cracking and non-bonding at the corners.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple device dies are integrated in the same package to achieve more functions, then device performance and functionality are improved, but cracking and non-bonding issues occur at the corners due to thermal expansion mismatch

Engineering Contradiction:
Improvedevice functionalityVSAvoidbonding reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The seal ring is segmented into two distinct portions: a first seal ring portion and a second seal ring portion. Each portion is made of different materials with different thermal expansion coefficients, allowing the structure to accommodate thermal stresses from multiple device dies with different technologies while maintaining bonding reliability at the corners

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the seal ring have different material compositions tailored to their specific locations. The first seal ring portion has a first material composition while the second seal ring portion has a second material composition, enabling each region to locally adapt to the thermal expansion characteristics of adjacent device dies, thereby preventing cracking and non-bonding issues

Inventive Principle:
Principle #3Local quality

2Reliability

If seal rings are made of materials with different thermal expansion coefficients to accommodate thermal mismatch, then stress-induced cracking is reduced, but the structure becomes more complex

Engineering Contradiction:
Improvecracking resistanceVSAvoidseal ring structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The seal ring is divided into two functional segments with different material compositions. This segmentation allows each portion to be optimized for its specific thermal environment while maintaining a relatively simple overall structure that integrates seamlessly into the package

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The seal ring utilizes composite material construction with at least two different materials having different thermal expansion coefficients. This composite approach enables the seal ring to handle thermal expansion mismatch from multiple device dies while maintaining structural integrity and avoiding cracking, without requiring overly complex geometric designs

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively minimizes stress-induced cracking and non-bonding issues by utilizing seal rings with varying thermal expansion coefficients, ensuring reliable bonding and improved package integrity.

Implementation Method 1

cracking and non-bonding issues at the corners due to thermal expansion mismatch between different materials, particularly at the interface of seal rings

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250343072A1Semiconductor package including step seal ring and methods forming same
Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250343072A1 patent drawing
  • US20250343072A1 patent drawing
  • US20250343072A1 patent drawing

AI summary

A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.