Step-Type Substrate for Thin Semiconductor Package Stacking
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Solution Overview
Problem
Current technologies face limitations in integrating high-capacity semiconductor chips within a smaller form factor without increasing the package thickness, necessitating innovative solutions for efficient chip stacking and mounting.
Innovation Solution
A semiconductor package design featuring a step-type substrate with recessed areas for flip-chip bonding of multiple semiconductor chips, ensuring stable and thin packaging by minimizing overhang and optimizing chip placement and bonding structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then chip integration is improved, but package thickness increases
Solution Approach 1:
The substrate is designed with a recess formed in the first face, creating a stepped structure that allows chips to be mounted at different vertical levels. This dimensional variation enables multiple chips to be integrated without simply stacking them vertically, thereby increasing chip integration while controlling package thickness.
Solution Approach 2:
The substrate has different local heights due to the recess, creating zones with different mounting surfaces. The first chip is mounted at the bottom of the recess while the second chip is mounted on the higher second face, allowing each chip to be positioned optimally without increasing overall package thickness.
2Ease of manufacture
If chips are mounted on a flat substrate, then manufacturing is simple, but structural stability deteriorates due to overhang
Solution Approach 1:
By introducing a recess in the substrate, the mounting surface is raised to match the height of overhanging chips. This eliminates the overhang condition that causes structural instability while maintaining the simplicity of the manufacturing process, as the recess is formed during substrate fabrication.
3Length of stationary object
If package thickness is reduced, then compact form factor is achieved, but chip stacking capability is limited
Solution Approach 1:
The substrate provides different local mounting heights: a lower region with the recess for the first chip and a higher region (second face) for the second chip. This allows two chips to be mounted within a limited vertical space, achieving compact form factor while maintaining chip stacking capability.
Data Source
AI summary
Disclosed herein are semiconductor packages. A semiconductor package may include a substrate configured to include a first face and a second face opposite the first face and to have a recess formed in the first face. The semiconductor package may include a first semiconductor chip disposed on the bottom of the recess. The semiconductor package may include a second semiconductor chip disposed on the second face of the substrate. The semiconductor package may include a third semiconductor chip disposed over the first face of the substrate and the first semiconductor chip. The semiconductor package may include a fourth semiconductor chip disposed over the third semiconductor chip.