Stepped Alignment Marks for Semiconductor Layer Precision
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Solution Overview
Problem
The increasing complexity and compactness of pattern designs in semiconductor devices require more precise alignment between layers to prevent defects such as abnormal contact, short circuits, or disconnection in integrated circuit structures, necessitating improved alignment marks and manufacturing processes.
Innovation Solution
The formation of semiconductor devices with stepped alignment marks in a dielectric layer ensures accurate positioning of interconnection structures by using first and second alignment marks with specific lateral edges, allowing for precise alignment and non-interference between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional alignment marks are used in photolithography, then the manufacturing process can be completed, but the alignment precision between upper and lower layers deteriorates as pattern designs become more compact
Solution Approach 1:
The alignment mark is divided into multiple segments including a first alignment mark in the first dielectric layer, a second alignment mark in the second dielectric layer, and a third alignment mark in the third dielectric layer. Each segment has specific lateral edges that serve as alignment references for different lithography steps, enabling precise alignment across multiple layers despite increasing pattern complexity.
Solution Approach 2:
The alignment structure extends into the vertical dimension by stacking alignment marks in multiple dielectric layers at different heights. The first, second, and third alignment marks are positioned at different vertical levels, creating a three-dimensional alignment reference system that provides precise alignment information for both planar and vertical positioning.
2Manufacturing precision
If alignment marks are added to improve alignment precision, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The multi-layer alignment mark structure serves multiple functions simultaneously: the first alignment mark provides reference for initial lithography steps, the second alignment mark provides reference for intermediate steps, and the third alignment mark provides reference for final steps. This universal alignment system handles all alignment requirements across different manufacturing stages, improving precision without proportionally increasing complexity.
Solution Approach 2:
The alignment marks are formed in advance during the dielectric layer deposition process, before the actual interconnection structures are fabricated. The first, second, and third alignment marks are created as part of the dielectric layer formation sequence, establishing precise alignment references beforehand that guide subsequent lithography and etching operations.
3Manufacturing precision
If stepped structure alignment marks are used, then alignment precision improves, but manufacturing process complexity increases
Solution Approach 1:
The formation of alignment marks is merged with the dielectric layer deposition process. The first alignment mark is formed with the first dielectric layer, the second alignment mark with the second dielectric layer, and the third alignment mark with the third dielectric layer. This integration combines alignment mark fabrication with routine dielectric processing, improving alignment precision while minimizing additional manufacturing steps.
Data Source
AI summary
A semiconductor device, a method of forming the same and a method of measuring the same are disclosed. The semiconductor device includes a substrate, a first dielectric layer, first alignment marks, a second dielectric layer and second alignment marks. The first dielectric layer is arranged on the substrate, the first alignment marks are arranged in the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second alignment marks are arranged in the second dielectric layer and spaced apart from each other, each having a stepped structure. The first and second alignment marks do not interfere with each other. A precisely positioned interconnection structure can thus be defined in the semiconductor device.