Stepped Backside Source/Drain Contacts for Dense Semiconductor Power Mesh
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Solution Overview
Problem
The increasing complexity and density of semiconductor integrated circuits (ICs) lead to issues with power dissipation and operational performance due to smaller metal lines, which result in worse resistance and processing speed wastage, particularly in Vdd and Vss power routing, causing RC delay and IR drop, and misalignment of back-side power conductive contacts with source/drain regions.
Innovation Solution
A metal line routing method is introduced where back-side power conductive contacts self-align with the source/drain regions by inheriting the location of the dielectric layer underlying the source/drain region, allowing for improved contact resistance and scaling of contacted poly pitch, and featuring a stepped sidewall structure with a wider back-side portion to connect back-side power metal layers, thereby reducing unwanted connections and enhancing operational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If functional density is increased and geometry size is decreased, then production efficiency is improved and costs are lowered, but power dissipation increases and contact resistance worsens
Solution Approach 1:
The patent introduces a stepped sidewall structure that extends the contact into a third dimension, creating multiple levels (first level and second level) with different lateral dimensions. The wider second level provides improved contact area and reduced resistance, while the stepped configuration maintains compatibility with scaled-down planar dimensions, thus resolving the contradiction between miniaturization and contact quality.
Solution Approach 2:
The contact structure is nested within the semiconductor device architecture, with the stepped contact positioned to receive metal layers and connect to source/drain regions. The contact structure embeds multiple functional levels within the vertical space, allowing improved electrical connection without increasing the overall device footprint, thereby maintaining high functional density while reducing contact resistance.
2Area of stationary object
If metal lines are made smaller to increase density, then more circuits fit on chip, but resistance increases and processing speed decreases
Solution Approach 1:
The stepped contact structure applies local quality enhancement at the critical contact region where electrical connection occurs. By providing a wider second level specifically at the contact interface, the structure optimizes local electrical properties (reduced resistance) without requiring all metal lines across the chip to be enlarged, thus maintaining overall high density while improving speed at critical paths.
3Reliability
If back-side power conductive contacts are formed, then power distribution is improved, but misalignment with source/drain regions occurs causing unwanted connections
Solution Approach 1:
The stepped contact structure is configured to self-align with the source/drain regions through its geometric configuration and positioning within the device architecture. The contact's lateral dimensions and vertical levels are designed to naturally interface with the source/drain regions without requiring additional alignment steps, enabling the contact to self-position correctly and prevent unwanted connections while maintaining improved power distribution.
Data Source
AI summary
A method includes forming semiconductor sheets on a front-side of a semiconductive layer on a front-side of a substrate; forming a gate strip surrounding each of the semiconductor sheets; forming dielectric layers on the semiconductive layer and at opposite sides of the gate strip; forming source/drain structures on the dielectric layers and on either side of each of the semiconductor sheets; performing a planarization process on a back-side of the substrate to expose the semiconductive layer; etching the semiconductive layer from a back-side of the semiconductive layer to form a first opening exposing a first one of the dielectric layers, while remains covering a second one of the dielectric layers; selectively removing the first one of the dielectric layers through the first opening to from a second opening exposing one of the source/drain structures; forming a contact having back-side and front-side portions in the first and second openings.