Stepped BGA Power Channel for Uniform Die Supply Current
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Solution Overview
Problem
High-power semiconductor devices face issues with non-uniform current distribution in BGA packages, leading to electromigration and bottlenecks due to excessive current flow through outermost balls, which reduces the maximum acceptable current and violates specifications.
Innovation Solution
A power channel design with a progressively decreasing ball-to-die resistance is achieved by utilizing a stack of planes on multiple layers connected via vias, forming a stepped structure where the number of planes and vias are adjusted based on current levels, ensuring even current distribution across the power channel balls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform plane connection is used in BGA packages, then the structure is simple and easy to manufacture, but the current distribution becomes non-uniform causing electromigration issues and bottlenecks in outermost balls
Solution Approach 1:
The power plane is segmented into multiple sections with different resistance values. Specifically, the plane is divided into a first section with a first resistance value and a second section with a second resistance value, where the first resistance value is greater than the second resistance value. This segmentation creates a progressive resistance decrease from outer to inner balls, ensuring uniform current distribution across all power balls and eliminating the bottleneck effect in outermost balls.
Solution Approach 2:
Different regions of the power plane are assigned different resistance characteristics to match the local current distribution requirements. The outer regions (first section) have higher resistance to reduce current density, while inner regions (second section) have lower resistance to facilitate current flow to the die. This local quality variation optimizes current distribution throughout the entire power channel structure.
2Reliability
If the resistance is decreased towards the die area, then current distribution improves, but the structure becomes more complex with multiple plane layers and vias
Solution Approach 1:
The resistance variation is achieved not only through planar geometry changes but also by utilizing the vertical dimension with multiple plane layers. Different plane layers (first plane layer, second plane layer, third plane layer) are connected through vias to form a three-dimensional progressive resistance structure. This allows resistance control in multiple directions and provides additional degrees of freedom for optimizing current distribution while managing complexity.
Solution Approach 2:
Multiple plane layers are nested vertically, with each layer contributing to the progressive resistance decrease. The first plane layer, second plane layer, and third plane layer are stacked and interconnected through vias, creating a nested structure where each layer serves a specific resistance function. This nesting approach consolidates multiple resistance-control functions into a compact vertical arrangement.
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A semiconductor device comprises a semiconductor die mounted at a die area (14) of a package (10) such as a BGA package with an array of electrically conductive balls (12) providing electrical contact for the semiconductor die. A power channel (16) is provided to convey power supply current towards the semiconductor die (14). The power channel (16) comprises a stack of electrically conductive planes (12A) between a current inflow plane (L8) opposite the die area (14) and a current outflow plane (L3) towards the die area (14). A distribution of electrically conductive balls (12) is coupled to the current inflow plane (L8) of the power channel (16) so that the power channel (16) provides current conduction paths towards the die area (14) for electrically conductive balls (12) in that distribution. Adjacent electrically conductive planes (12A) in the stack of the power channel (16) are electrically coupled with electrically conductive vias (120) extending therebetween. The electrically conductive planes (12A) are stacked in a stepped arrangement (Step1, Step2, Step3, Step4) wherein the number of stacked planes (12A) increases in steps in the direction from the distal end (PE) to the proximal end of the power channel (16). The current conduction paths towards the die area (14) thus have resistance values that decrease from the distal end (PE) to the proximal end of the power channel (16). A uniform distribution of power supply current over the length of the power channel (16) is thus facilitated.