Stepped Chip Structure Layout for Void-Resistant Semiconductor Packaging
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Solution Overview
Problem
Semiconductor packages for high-performance computing face challenges with warpage and voids due to narrow spaces between chips, which affect the encapsulant's integrity and yield.
Innovation Solution
The semiconductor package design includes a substrate with multiple chip structures of varying thicknesses, where a lower chip structure overlaps part of the space between adjacent chips and an upper chip structure exposes another part, facilitating unimpeded encapsulant flow and reducing warpage and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor chips are mounted adjacent to each other on the same substrate to achieve high performance computing, then the computing performance is improved, but warpage and voids occur in the encapsulant due to narrow spaces between chips
Solution Approach 1:
The third chip structure is divided into a lower chip structure and an upper chip structure stacked in the thickness direction. This segmentation allows the lower chip structure to overlap a first portion of the space between adjacent chips while the upper chip structure exposes a second portion, creating a stepped configuration that prevents encapsulant voids while maintaining narrow pitch for high performance computing
Solution Approach 2:
The invention transitions from a two-dimensional planar arrangement of chips to a three-dimensional stacked configuration. By stacking the lower and upper chip structures vertically, the design utilizes the thickness direction to resolve the contradiction between maintaining narrow horizontal spacing for performance and preventing encapsulant defects through vertical differentiation
2Quantity of substance
If the space between adjacent chip structures is reduced to increase chip density, then chip density is improved, but warpage and voids occur in the encapsulant
Solution Approach 1:
Different regions of the chip structure are given different heights in the thickness direction. The lower chip structure has a first thickness while the upper chip structure has a second thickness greater than the first, creating local quality variations that allow the structure to maintain high chip density while preventing encapsulant voids in specific regions through the stepped configuration
3Device complexity
If uniform thickness chip structures are used for simplicity, then device complexity is reduced, but warpage occurs in the encapsulant due to narrow spaces between chips
Solution Approach 1:
The chip structures are designed with asymmetric thicknesses where the upper chip structure has a greater thickness than the lower chip structure. This asymmetric design creates a stepped configuration that breaks the uniformity causing warpage, while the overall layout remains systematic and manufacturable
Data Source
AI summary
A semiconductor package includes a substrate; a first chip structure on the substrate and having a first thickness in a first direction; a second chip structure on the substrate adjacent to the first chip structure along a second direction and having a second thickness in the first direction; a third chip structure on the substrate and adjacent to the first chip structure and the second chip structure in a third direction perpendicular to the second direction; and an encapsulant covering the first chip structure, the second chip structure, and the third chip structure, wherein the third chip structure includes a lower chip structure that overlaps a first portion of a space between the first chip structure and the second chip structure in the third direction, and an upper chip structure on the lower chip structure such that a second portion of the space is exposed in the third direction.