Stepped Chip Stack Wiring for Compact Semiconductor Packages
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Solution Overview
Problem
There is a need for semiconductor packages that reduce size and weight while maintaining excellent electrical characteristics, particularly for high-frequency signals, as portable devices demand compactness and improved electrical performance.
Innovation Solution
A semiconductor package design featuring a substrate with power/ground pads and input/output pads, a stacked chip structure with ascending stepwise semiconductor chips, and specific wire connections that directly link pads between chips and the substrate, enhancing electrical coupling and stability through multiple connection paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are sequentially stacked on a PCB with bonding wires for electrical connection, then the package structure is established, but the size and weight reduction required for portable devices is insufficient
Solution Approach 1:
The patent transitions from planar arrangement of chips on a PCB to a three-dimensional stacked configuration where multiple semiconductor chips are vertically arranged. This vertical stacking in the third dimension significantly reduces the footprint area while maintaining electrical connection reliability through direct pad-to-pad coupling between adjacent chips, eliminating the need for long bonding wires that extend across the PCB surface.
Solution Approach 2:
The invention extracts and eliminates the bonding wire interconnection layer from the traditional package structure. By directly coupling pads between adjacent stacked chips, the patent removes the intermediate bonding wire elements, thereby reducing overall package size and weight while improving electrical characteristics by shortening current paths and reducing parasitic inductance.
2Reliability
If bonding wires are used to connect connection pads of stacked semiconductor chips, then electrical coupling is achieved, but electromagnetic wave interference increases and electrical characteristics deteriorate
Solution Approach 1:
The patent converts the potential harm of long current paths (which cause electromagnetic interference) into benefit by reconfiguring the electrical connection architecture. Instead of using long bonding wires that act as antennas for electromagnetic radiation, the invention creates short direct pad-to-pad connections between stacked chips, transforming the connection path from a harmful radiating element into a beneficial low-inductance current path that minimizes electromagnetic interference.
Solution Approach 2:
The invention extracts and removes the bonding wire interconnection mechanism from the package structure. By eliminating bonding wires entirely and implementing direct pad coupling between adjacent stacked chips, the patent removes the primary source of electromagnetic wave interference while maintaining reliable electrical characteristics through shortened current paths and reduced parasitic effects.
3Volume of moving object
If multiple individual devices are integrated on a single package, then size reduction is achieved, but the complexity of wire connections and channels increases
Solution Approach 1:
The patent segments the package into multiple independent stacked chip modules, each with its own pad array. This segmentation allows each chip to be independently connected to adjacent chips through direct pad coupling, simplifying the connection structure compared to a monolithic integrated device. The modular segmented approach reduces overall complexity while enabling multi-device integration in a compact vertical arrangement.
Solution Approach 2:
The invention resolves connection complexity by transitioning from two-dimensional planar routing to three-dimensional vertical stacking. Multiple devices are integrated along the vertical axis rather than spread out horizontally, with direct pad-to-pad connections between adjacent stacked chips. This dimensional change simplifies interconnections by eliminating the need for complex lateral wire routing across the package, as each chip connects directly to its neighbors in the stack.
Data Source
AI summary
Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.