Stepped Clocking Frequency Mode for Processor Cores
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Solution Overview
Problem
Integrated circuits (ICs) face performance limitations due to increased heat generation from higher clocking frequencies and voltages, leading to reduced efficiency and longevity, with existing thermal mitigation systems often resulting in slower operation to prevent overheating, which can prolong workload execution and increase power consumption.
Innovation Solution
A stepped clocking frequency mode that alternates between two or more frequency levels to maintain higher average performance while reducing thermal load, allowing the processor to operate at higher frequencies for short bursts and lower frequencies to dissipate heat, thus delaying thermal mitigation events and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clocking frequency is increased to improve IC performance, then the processing speed increases, but the heat generation and temperature increase
Solution Approach 1:
The patent implements periodic action by alternating between high-frequency and low-frequency clocking modes in a stepped pattern. The IC operates at high frequency for predetermined time intervals to achieve maximum performance, then transitions to lower frequencies to dissipate heat, creating a periodic cycle that balances performance and thermal management.
Solution Approach 2:
The patent applies dynamics by making the clocking frequency adjustable and time-dependent rather than fixed. The system dynamically transitions between multiple frequency levels based on predetermined time intervals, allowing the IC to adapt its operating frequency to balance performance requirements with thermal constraints.
2Productivity
If the clocking frequency is increased to improve performance, then the processing speed increases, but the power consumption increases
Solution Approach 1:
The patent uses periodic action to alternate between high-power high-frequency operation and lower-power low-frequency operation. By scheduling high-frequency bursts followed by lower-frequency intervals, the system achieves high productivity when needed while reducing average power consumption through periodic low-power states.
Solution Approach 2:
The patent applies partial action by operating at maximum frequency only for portions of the total operation time rather than continuously. The stepped clocking mode uses high-frequency operation partially for predetermined intervals, accepting that not all time is spent at maximum performance to reduce overall power consumption.
3Temperature
If thermal mitigation is applied to reduce temperature, then the IC temperature decreases, but the clocking frequency must be reduced
Solution Approach 1:
The patent implements periodic thermal mitigation by alternating between high-frequency operation and lower-frequency cooling intervals. Instead of continuously reducing frequency for thermal mitigation, the system periodically allows high-frequency operation followed by controlled lower-frequency intervals that serve as thermal mitigation periods, achieving both goals cyclically.
Solution Approach 2:
The patent applies dynamics by making thermal mitigation time-dependent rather than continuous. The clocking frequency is dynamically adjusted based on predetermined time intervals, allowing the IC to transition between high-performance states and thermal mitigation states, optimizing both temperature control and performance utilization.
4Productivity
If the IC operates at maximum frequency to meet processing demands, then the processing performance increases, but the operational duration is limited by thermal constraints
Solution Approach 1:
The patent uses periodic action to extend operational duration by cycling between high-performance intervals and thermal recovery intervals. The IC operates at maximum frequency for predetermined high-performance periods, then transitions to lower frequencies for thermal management, allowing sustained operation over extended periods rather than being limited to short maximum-frequency bursts.
Solution Approach 2:
The patent applies dynamics by making the operational mode time-dependent, allowing the IC to adapt between performance-maximizing and thermal-managing states. This dynamic stepped clocking approach enables the system to maintain high productivity during critical intervals while extending overall operational duration through controlled lower-frequency periods.
Data Source
AI summary
Aspects relate to a stepped clocking frequency mode for integrated circuit components. An apparatus includes a processor core configured to perform operations at a received clocking frequency and a clock controller. The clock controller is configured to clock the processor core with a default frequency in response to the processor core operating in a default mode of operation, and, responsive to a parameter value associated with the processor core exceeding a first threshold, to enter a stepped clocking frequency mode, that includes alternating between clocking the processor core at a first frequency for a first time interval, and clocking the processor core at a second frequency different than the first frequency for a second time interval.