Stepped Conductive Layers in Nonvolatile Semiconductor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices with cylindrical column-type transistors face challenges in reducing occupied area due to stepped conductive layers beyond the memory string region, limiting integration density and increasing manufacturing complexity.
Innovation Solution
A nonvolatile semiconductor memory device design featuring a stepped conductive layer configuration at the memory string region's periphery, where the ends of conductive layers differ in position, and a wall-like alignment of peripheral conductive layers, optimizing the use of space and reducing the occupied area by allowing for more efficient contact plug formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the stacked conductive layer is formed in a stepped shape to form contact plugs, then contact plug formation is enabled, but the occupied area of the semiconductor memory device increases
Solution Approach 1:
The patent divides the conductive layers into two distinct groups: first conductive layers (31a-31d) that form the stepped portion at the memory string region, and second conductive layers (71a-71d) that form the wall portion in the peripheral region. This segmentation allows each region to have optimized geometry - the stepped shape where needed for contact plugs, and the aligned wall shape where space efficiency is critical.
Solution Approach 2:
The patent applies different geometric configurations to different spatial regions: the memory string region uses stepped conductive layers to enable contact plug formation, while the peripheral region uses aligned conductive layers to minimize occupied area. This local optimization ensures that the stepped shape is only used where functionally necessary.
2Ease of manufacture
If the stacked conductive layer is formed in a stepped shape throughout, then contact plug formation is simplified, but the degree of integration is reduced
Solution Approach 1:
The conductive layers are segmented into first conductive layers for the memory string region and second conductive layers for the peripheral region. This segmentation enables the stepped configuration to be localized only where contact plugs are needed, while the peripheral region maintains a compact aligned structure that supports higher integration density.
Solution Approach 2:
The patent transitions from a uniform two-dimensional stepped layout to a three-dimensional configuration where the conductive layers are divided into multiple functional groups with different geometries. This dimensional complexity allows simultaneous optimization of contact plug formation in one region and space efficiency in another.
3Ease of manufacture
If the stacked conductive layer is formed in a stepped shape, then contact plug formation is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent segments the conductive layers into first and second groups with distinct functions and geometries. This segmentation simplifies the manufacturing process by allowing each group to be formed with a configuration optimized for its specific purpose, rather than requiring a complex uniform stepped structure throughout the entire device.
Solution Approach 2:
The manufacturing process is simplified by applying local quality principles: the stepped shape is used only in the memory string region where contact plugs are formed, while the peripheral region uses a simpler aligned wall configuration. This reduces the overall manufacturing complexity compared to a fully stepped structure.
Data Source
AI summary
A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.