Stepped Conductive Via for High Density RDL
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve high via density and prevent overhang issues in redistribution layers (RDL) of integrated circuits, particularly as via holes are scaled down, requiring innovative structural designs for conductive vias.
Innovation Solution
A semiconductor structure with conductive vias featuring a stepped profile, including a bottom portion, a tapered portion, and a top portion, where the tapered and top portions are wider than the bottom portion, allowing for improved via density and mitigating overhang problems during metal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If via holes are scaled down to achieve miniaturization, then circuit density is improved, but overhang issues occur during metal deposition
Solution Approach 1:
The conductive via is divided into three distinct segments: a bottom portion, a tapered portion, and a top portion. This segmentation allows each portion to serve a specific function - the narrower bottom portion enables higher density while the wider top portion prevents overhang during metal deposition, resolving the technical contradiction between miniaturization and manufacturing precision.
Solution Approach 2:
The conductive via employs an asymmetric stepped profile where the top portion is wider than the bottom portion. This asymmetric design creates sufficient lateral support at the top to prevent metal overhang during deposition while maintaining the compact bottom portion for high via density, thereby solving the contradiction between circuit density and overhang control.
2Volume of moving object
If via holes are scaled down to achieve miniaturization, then device size is reduced, but via density improvement is limited by overhang problems
Solution Approach 1:
By segmenting the via into bottom, tapered, and top portions with different widths, the design achieves compact overall dimensions while the stepped profile enables improved via density. The segmentation allows the via to be smaller than conventional designs while preventing overhang, thus resolving the contradiction between device size and via density.
Solution Approach 2:
The stepped profile introduces a dimensional variation along the vertical axis of the via, creating width differences at different heights. This dimensional change allows the via to maintain small horizontal footprint for miniaturization while the vertical dimension provides the necessary structural support to prevent overhang, enabling improved via density without compromising manufacturing feasibility.
3Ease of manufacture
If conventional via structures are used, then manufacturing process is simple, but overhang issues prevent improved via density
Solution Approach 1:
The segmented stepped profile structure, while more complex than conventional uniform vias, can be formed using standard etching and deposition processes. The segmentation enables via density improvement by preventing overhang, and the process complexity is managed through conventional semiconductor manufacturing techniques, resolving the contradiction between ease of manufacture and via density.
Data Source
AI summary
A semiconductor structure includes a semiconductor device, an interconnect structure, a dielectric layer, and a redistribution layer (RDL). The interconnect structure is disposed over the semiconductor device. The dielectric layer is disposed over the interconnect structure. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via includes a bottom portion, a top portion and a tapered portion between the bottom and top portions, in which the tapered portion has a width variation greater than that of the bottom and top portions.