Stepped Contact Structure for Lower CMOS Parasitic Capacitance

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Solution Overview

Problem

Conventional CMOS device contact structures struggle to reduce parasitic capacitance between contacts and gates without increasing internal resistance, which limits operating speed and performance.

Innovation Solution

The proposed solution involves creating a semiconductor die with a contact structure that includes a first portion with a larger cross-sectional area and a second portion with a smaller cross-sectional area, featuring a lower and upper portion, where the upper portion has a narrower width and height, and is either surrounded by insulating material or an air gap, to reduce parasitic capacitance while maintaining acceptable internal resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a portion of the contact structure is removed to reduce the parallel area between contact and gate, then parasitic capacitance is reduced, but internal resistance increases

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidinternal resistance

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The contact structure is divided into two distinct portions: a first portion with a first cross-sectional area and a second portion with a second cross-sectional area that is less than the first. This segmentation allows different regions of the contact to serve different functions - the larger first portion maintains low internal resistance while the smaller second portion reduces parasitic capacitance with the gate structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different cross-sectional areas are assigned to different portions of the contact structure based on their specific functional requirements. The first portion has a larger cross-sectional area optimized for current conduction (low resistance), while the second portion has a smaller cross-sectional area optimized for reducing capacitive coupling with the gate. This local differentiation of properties resolves the contradiction between resistance and capacitance.

Inventive Principle:

Principle #3Local quality

2Speed

If more of the contact structure is removed to further reduce parasitic capacitance, then operating speed increases, but the risk of electrical open condition increases

Engineering Contradiction:

Improveoperating speedVSAvoidelectrical open condition

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

Instead of removing a large portion of the contact structure (which would risk electrical open), the invention applies partial action by removing only a controlled second portion while maintaining the first portion with sufficient cross-sectional area. This partial removal achieves enough capacitance reduction to improve operating speed while maintaining adequate conductive path to prevent electrical open conditions.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If the height of the remaining contact structure is increased to maintain low internal resistance after removal, then resistance is maintained, but the reduction in parasitic capacitance becomes insignificant

Engineering Contradiction:

Improveinternal resistanceVSAvoidparasitic capacitance reduction

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Instead of compensating for reduced cross-sectional area by increasing height (vertical dimension only), the invention introduces a horizontal dimension by creating a two-tiered cross-sectional structure. The contact transitions from a uniform cross-section to a stepped cross-section with different areas at different vertical levels, utilizing both vertical and horizontal spatial dimensions to simultaneously optimize resistance and capacitance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP4205169B9Optimized contact structure and methods of its manufacture

Publication Date: 2024.07.03 QUALCOMM INC

Figure 1A~1B
Figure 2A~2C(iv)
Figure 3A~3C(iv)

AI summary

Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.