Stepped Contact Vias for Dense Transistors With Low Contact Resistance
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Solution Overview
Problem
As semiconductor devices shrink, contact via structures for field effect transistors face scaling issues with decreased contact area and increased contact resistance due to the reduction in lateral dimensions of source and drain regions.
Innovation Solution
The implementation of stepped contact via structures that vertically extend through a stack of proximal and distal dielectric material layers, with the lower portions of the contact via cavities laterally expanded using an isotropic etch process to increase the contact area with active regions, ensuring low contact resistance and avoiding electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the lateral dimensions of source regions and drain regions are decreased to increase device density, then the device density increases, but the contact area decreases and contact resistance increases
Solution Approach 1:
The contact via structure transitions from a simple vertical cylinder to a stepped structure with multiple horizontal levels. The first contact via portion extends deeper into the active region while the second contact via portion provides additional lateral contact area at a higher level, effectively utilizing the vertical dimension to maintain contact area despite reduced lateral dimensions of the active region
Solution Approach 2:
The contact via structure is divided into two distinct portions: a first contact via portion that extends vertically to contact the active region, and a second contact via portion that extends laterally at a higher level. This segmentation allows each portion to fulfill different functions - the first portion provides deep contact while the second portion provides additional contact area without increasing the overall footprint
2Reliability
If the contact via structure size is increased to maintain contact area, then the contact resistance decreases, but the device density decreases
Solution Approach 1:
Instead of increasing the lateral footprint of the contact via structure, the design extends the first contact via portion deeper into the active region along the vertical dimension. This maintains contact area and reduces contact resistance without increasing the lateral size, thereby preserving device density
Solution Approach 2:
The second contact via portion is positioned at a higher level and laterally offset from the first contact via portion, creating a nested-like configuration where the contact via structure occupies multiple vertical levels. This allows the contact area to be effectively increased through vertical stacking rather than lateral expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces contact resistance and increases the on-current of field effect transistors without increasing the size or pitch of the contact via structures, thereby enhancing device density.
Implementation Method 1
laterally expanding a lower portion of the first contact via cavity by etching the first dielectric material around the first contact via cavity selective to the second dielectric material
Data Source
AI summary
A transistor includes a semiconductor substrate including a first active region, a second active region, and a semiconductor channel, a gate stack structure that overlies the semiconductor channel, a proximal dielectric material layer overlying the semiconductor substrate, laterally surrounding the gate stack structure, a distal dielectric material layer overlying the proximal dielectric material layer, and a first contact via structure contacting the first active region having a greater lateral extent at a level of the proximal dielectric material layer than at a level of the distal dielectric material layer.