Stepped Contacts for Vertical Memory Interconnection
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Solution Overview
Problem
The interconnection layout of vertical memory devices poses challenges, as direct connection to the source or drain can cause electrical shorts, while routing connections to the periphery increases bit line resistance, necessitating a solution that maintains bit line resistance and chip area efficiency.
Innovation Solution
A method involving a substrate with alternating first and second blocks, where stack structures with semiconductor layers are formed, and stepped contacts are created to connect semiconductor layers without shorting, using conductive lines that extend between stack structures to maintain electrical insulation and efficient interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the interconnection layout directly connects to the source or drain of the memory device, then the chip area is reduced, but the source and drain become electrically connected causing device failure
Solution Approach 1:
The substrate is divided into alternating first blocks and second blocks, with each block containing specific regions that are selectively connected. This segmentation allows the interconnection to access source and drain regions without creating direct electrical paths between adjacent memory cells, thus preventing shorts while maintaining compact chip area.
Solution Approach 2:
Different regions of the substrate are assigned different functions: first blocks contain first regions for specific connections, second blocks contain second regions for other connections. This local differentiation enables precise control over electrical connectivity, allowing direct access to source/drain in certain areas while maintaining isolation in others.
2Reliability
If the interconnection layout is routed to the periphery region to connect source and drain, then electrical isolation is improved, but the bit line resistance increases
Solution Approach 1:
Instead of routing interconnections only in the planar direction (periphery), the patent utilizes vertical stacking with multiple semiconductor layers and conductive layers at different heights. This three-dimensional interconnection approach allows direct access to source and drain regions without long lateral paths, reducing resistance while maintaining isolation through vertical separation and selective connectivity.
3Reliability
If vertical memory devices are used to reduce short channel effects, then device performance is improved, but interconnection problems arise between source and drain
Solution Approach 1:
The patent employs a nested structure with multiple semiconductor layers (first, second, third semiconductor layers) and corresponding conductive layers embedded within each other vertically. The first conductive layer connects to source/drain in the first semiconductor layer, while second and third conductive layers provide additional connectivity levels. This nested arrangement enables complex interconnection functionality within a compact vertical footprint, managing the complexity through hierarchical organization rather than lateral expansion.
Data Source
AI summary
A memory device is provided. The memory device includes a plurality of stack structures, a plurality of first stepped contacts, and a plurality of second stepped contacts. Each of the stack structures extends in a first direction, and includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is disposed above the first semiconductor layer. Each of the first stepped contacts extends in a second direction, and a bottom surface thereof is electrically connected to the first semiconductor layers of an i+1th stack structure and an i+2th stack structure, wherein i is an odd number. Each of the second stepped contacts extends in the second direction, and a bottom surface thereof is electrically connected to the second semiconductor layers of an nth stack structure and the i+1th stack structure. The first direction is different from the second direction.