Stepped Copper Layers Reduce Thermal Stress in DBC Substrates
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Solution Overview
Problem
High-power electronic devices using direct bonded copper (DBC) substrates face issues with delamination, cracking, and warpage due to coefficient of thermal expansion mismatches between ceramic and copper materials, making them prone to failure under temperature variations.
Innovation Solution
A circuit board design featuring electrically conductive layers with peripheral marginal regions in a stepped arrangement, where the first layer has a larger area dimension than the second layer but not greater thickness, to minimize stress caused by thermal expansion differences, and a method involving electroplating and photoresist patterning to achieve this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a thick copper layer is used to sustain high voltage and current, then the power handling capability is improved, but the CTE mismatch stress causes delamination and warpage
Solution Approach 1:
The copper layer is segmented into multiple sub-layers with different thicknesses. The first sub-layer has a greater thickness than the second sub-layer, creating a stepped configuration that reduces overall stress while maintaining power handling capability through the cumulative copper cross-section
Solution Approach 2:
Different regions of the copper structure have different thicknesses to optimize local stress distribution. The first sub-layer has greater thickness at specific regions to handle high current density, while the second sub-layer has reduced thickness to minimize CTE mismatch stress, creating a non-uniform but optimized stress distribution
2Reliability
If a sloping peripheral region is formed by etching to prevent delamination, then the delamination resistance is improved, but the manufacturing precision and mass production consistency deteriorate
Solution Approach 1:
The stepped configuration is built during the copper layer formation process itself, before final circuit patterning. By creating the thickness variation in the copper sub-layers during electroplating or lamination, the stress-reducing geometry is established in advance, eliminating the need for subsequent etching to create sloping edges
3Reliability
If multiple buffer layers with different materials are used to reduce stress, then the stress distribution is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The copper interlayer is used as the stress-management medium throughout the structure, maintaining material homogeneity. Both the first and second sub-layers are made of the same copper material, eliminating the need for heterogeneous buffer layers with different materials while still achieving stress distribution through geometric variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stepped configuration reduces delamination, cracking, and warpage, enabling mass production of stress-reduced circuit boards for high-power electronic devices, with improved reliability under temperature variations.
Implementation Method 1
a first copper layer is formed on the ceramic substrate, and a second copper layer is stacked on the first copper layer
Data Source
AI summary
A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.