Stepped Data Link Lines for Narrow Bezel Displays

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Solution Overview

Problem

Existing display devices face challenges in minimizing the bezel area while maintaining image quality due to coupling capacitance issues caused by data link lines in the display area, which affects the overall weight, size, and aesthetic appeal.

Innovation Solution

The implementation of a display panel with data link lines formed in a stepped line structure within the display area, reducing coupling capacitance and allowing for a narrower bezel and improved image quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If data link lines are disposed in the display area to reduce bezel width, then the bezel area is reduced and device size is minimized, but coupling capacitance between adjacent signal lines increases degrading image quality

Engineering Contradiction:
Improvebezel areaVSAvoidcoupling capacitance
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent applies dimensionality change by transitioning data link lines from a planar configuration to a three-dimensional stepped structure. The data link lines extend in multiple directions (first direction toward data driving circuit, second direction perpendicular thereto) forming steps that reduce coupling capacitance while maintaining compact bezel area. This spatial reconfiguration allows the lines to achieve both short path length and reduced electromagnetic interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the data link lines into multiple sections with different extension directions. Each segment extends in a specific direction (first direction or second direction perpendicular to it) to create a stepped pattern. This segmentation distributes the capacitance coupling across multiple smaller segments rather than one continuous line, reducing overall coupling capacitance while maintaining connectivity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If data link lines are extended further to connect to data driving circuit, then connection reliability is improved, but coupling capacitance with adjacent signal lines increases

Engineering Contradiction:
Improveconnection reliabilityVSAvoidcoupling capacitance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent uses three-dimensional stepped structure to extend data link lines further while managing capacitance. By extending lines in multiple directions (first direction for primary connection, second direction perpendicular for additional routing), the lines achieve greater connection reliability without proportionally increasing coupling capacitance, as the stepped geometry reduces parallel coupling length.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs asymmetric extension where different data link lines extend in different directions and to different degrees. Some lines extend more in the first direction toward the data driving circuit, while others extend more in the second perpendicular direction. This asymmetric configuration optimizes each line's path to balance connection reliability with minimized coupling capacitance based on its specific routing requirements.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20240292689A1Display device and display panel
Publication Date: 2024.08.29 LG DISPLAY CO LTD
  • US20240292689A1 patent drawing
  • US20240292689A1 patent drawing
  • US20240292689A1 patent drawing

AI summary

A display device and a display panel are discussed. In one example, the display device includes a data driving circuit to supply a plurality of data voltages to a plurality of data lines, wherein the plurality of data lines comprise first data lines and second data lines; a gate driving circuit to supply a plurality of gate signals to a plurality of gate lines; and a display panel having the first data lines disposed in a first area corresponding to the data driving circuit, and the second data lines disposed in a second area located outside of the first area. Further, the display panel can include first data link lines for connecting the first data lines to the data driving circuit, and second data link lines with connecting paths arranged in a stepped line configuration for connecting the second data lines to the data driving circuit.