Stepped Die Stack Interconnect for Thin Multi-Die Packaging
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Solution Overview
Problem
Conventional semiconductor packages with stacked dies face challenges in minimizing thickness due to the use of bond wires, which restrict the ability to incorporate multiple semiconductor dies while maintaining reliability and signal integrity.
Innovation Solution
The solution involves forming a semiconductor die stack with a pair of semiconductor dies, where one die is bonded on top of the other in an offset configuration, with conductive traces created using additive manufacturing to electrically couple the dies, eliminating the need for bond wires and allowing for multiple dies to be stacked without increasing package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bond wires are used to electrically interconnect stacked semiconductor dies, then multiple dies can be connected, but the package height increases
Solution Approach 1:
The patent transitions from vertical wire bonding (z-dimension) to lateral conductive trace routing (x-y plane) for electrical interconnection. Conductive traces are formed on the substrate to electrically connect contact pads of different dies laterally, eliminating the need for vertical bond wires and reducing package height while maintaining multi-die functionality
Solution Approach 2:
The patent removes bond wires from the package structure entirely, extracting the harmful element that increases height. Instead of using bond wires for electrical interconnection, the invention uses substrate-integrated conductive traces that route signals laterally beneath or alongside the die stack, eliminating the height penalty associated with wire bonding
2Length of stationary object
If flip-chip arrangement with bonding balls or bumps is used, then package thickness is minimized, but only a single semiconductor die can be used
Solution Approach 1:
The patent segments the electrical interconnection function between the dies and substrate: each die maintains its flip-chip bonding to the substrate for mechanical support and primary electrical connection, while additional dies are added in stacked configurations. Conductive traces on the substrate provide additional interconnection pathways that enable multiple dies to be electrically connected without compromising the thin profile achieved through flip-chip mounting
Solution Approach 2:
The substrate serves as an intermediary element that enables multi-die stacking while maintaining thin profile. Conductive traces on the substrate act as mediator pathways that electrically connect contact pads of multiple stacked dies to the substrate and to each other, allowing the flip-chip arrangement to support multiple dies rather than just a single die
3Adaptability or versatility
If bond wires are used for electrical interconnection, then multiple dies can be connected, but reliability is reduced due to risks of die cracking
Solution Approach 1:
The patent removes bond wires from the package structure, extracting the source of mechanical stress and reliability issues. By eliminating bond wires entirely and replacing them with substrate-integrated conductive traces, the invention removes the risk of wire-induced die cracking while maintaining the ability to electrically interconnect multiple stacked dies
Solution Approach 2:
The patent replaces the mechanical wire bonding system with an integrated circuit trace system. Instead of using physical wires that are bonded to die surfaces (mechanical connection prone to stress and cracking), the invention uses conductive traces formed on the substrate that provide electrical interconnection through a more integrated and mechanically robust pathway, reducing reliability concerns
Data Source
AI summary
A stacked chip scale semiconductor device includes one or more semiconductor die stacks. Each semiconductor die stack may include a pair of semiconductor dies. A first of the pair of semiconductor dies may be provided with a pattern of contact pads distributed across its major surface configured to be flip chip bonded to a host device. A second of the pair of semiconductor dies may include a row of contact pads. The first semiconductor die may be bonded on top of the second semiconductor die in an offset, stepped configuration so that the row of contact pads of the second semiconductor die is left exposed. Like channels of contact pads on the first and second semiconductor dies may then be electrically coupled by additive manufacturing or conductive trace printing.