Stepped Electrode Thin-Film Capacitor Design
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Solution Overview
Problem
Existing thin-film capacitors face challenges in increasing capacitance while minimizing thickness and reducing the number of connection electrode layers, which affects their efficiency and reworkability, especially in applications like decoupling capacitors for application processors.
Innovation Solution
A capacitor design featuring a substrate with trenches and dielectric layers, where first and second electrode layers are alternately disposed with a stepped lead portion configuration, reducing the number of connection electrode layers and enhancing capacitance by optimizing the surface area and connection geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin-film capacitor is designed with conventional parallel electrode layers, then the structure is simple and manufacturing is easy, but the capacitance is insufficient and the thickness cannot be reduced
Solution Approach 1:
The patent transitions from conventional parallel electrode layers to a three-dimensional stacked configuration where electrode layers are arranged vertically with alternating polarity. This dimensional change increases the effective capacitance area without increasing the planar footprint, thereby achieving higher capacitance in a thinner profile while maintaining manufacturing feasibility through standardized layer deposition processes
2Reliability
If multiple connection electrode layers are used to increase capacitance, then the capacitance increases, but the thickness increases and the number of manufacturing steps increases
Solution Approach 1:
The patent stacks electrode layers vertically in the thickness direction rather than expanding them horizontally. By alternating positive and negative electrode layers in the vertical dimension with dielectric layers interspersed, the design achieves increased capacitance through greater layer density without proportionally increasing overall thickness, as each stacked unit contributes to capacitance while maintaining a compact vertical profile
Solution Approach 2:
The patent implements a nested structure where dielectric layers are positioned between and insulating electrode layers, creating a compact stacked arrangement. This nesting allows multiple functional layers to occupy the same vertical space efficiently, increasing capacitance per unit thickness while minimizing the overall device thickness through optimized layer integration
3Area of stationary object
If a land-side capacitor form factor is used to decrease solder ball removal area, then the capacitor size is reduced, but the capacitance density decreases
Solution Approach 1:
The patent compensates for the reduced planar area of the land-side capacitor form factor by stacking multiple electrode and dielectric layers vertically. This three-dimensional arrangement concentrates the capacitance-generating structure in the thickness direction, achieving high capacitance density within a small footprint that is compatible with compact land-side mounting and minimizes solder ball removal area
Data Source
AI summary
A capacitor includes: a substrate including a plurality of trenches and a capacitance formation portion, and a margin portion disposed around the capacitance formation portion; dielectric layers disposed on one surface of the substrate and filling the trenches; a plurality of first electrode layers each disposed on one surface of the dielectric layer and each including a first lead portion led out from the capacitance formation portion to the margin portion; and a plurality of second electrode layers each disposed on one surface of the dielectric layer to face the first electrode layer with each of the dielectric layers interposed therebetween, and each including a second lead portion led out from the capacitance formation portion to the margin portion, wherein the first and second lead portions of the plurality of first and second electrode layers are stacked in a stepped shape inclined in a direction from the margin portion to the capacitance formation portion.