Stepped Field Plate GaN FET Layout for Breakdown and Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GaN-based HEMTs with gate-to-drain field plates exhibit poor reliability, particularly at class C operation, due to significant electric fields on the source side of the gate, leading to high-field trapping effects and reduced breakdown voltage.
Innovation Solution
A transistor device with a multiple-stepped field plate that is laterally spaced apart from the gate, featuring a recessed portion above an aperture in the surface dielectric layer, and stepped portions vertically spaced from the semiconductor barrier layer with increasing distances, allowing for reduced gate-to-drain capacitance and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a gate-to-drain field plate is used, then breakdown voltage is increased and high-field trapping effect is reduced, but reliability deteriorates due to significant electric fields on the source side of the gate
Solution Approach 1:
The field plate is divided into multiple segments: a first field plate segment positioned over the drain region and a second field plate segment positioned over the source region, separated by a gap. This segmentation allows independent optimization of electric field control in different regions, reducing the harmful electric field concentration on the source side while maintaining the breakdown voltage enhancement effect on the drain side.
Solution Approach 2:
Different regions of the device are provided with different field plate configurations tailored to their specific needs. The drain region receives a field plate segment optimized for breakdown voltage enhancement, while the source region receives a separate field plate segment optimized for electric field reduction, allowing localized optimization of electrical characteristics.
2Power
If a field plate is connected to the source, then gate-to-drain capacitance is reduced and gain is enhanced, but linearity deteriorates and drain bias dependence increases
Solution Approach 1:
The field plate structure is segmented into distinct portions that can independently influence different electrical characteristics. The first field plate segment primarily affects gate-to-drain capacitance and breakdown voltage, while the second field plate segment influences gate-to-source capacitance and linearity, allowing separate optimization of these competing parameters.
Solution Approach 2:
The gap between the first and second field plate segments acts as an intermediary region that mediates the electric field distribution. This gap allows the field plate structure to reduce gate-to-drain capacitance while simultaneously reducing the harmful electric field effects on the source side, thereby improving linearity without sacrificing gain.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed transistor device achieves enhanced reliability and performance by reducing gate-to-drain capacitance, increasing breakdown voltage, and improving linearity, particularly at high power and high frequency operations.
Implementation Method 1
the field plate 28 extends above the gate 26 and laterally toward the drain contact 24. The field plate 28 is connected to the source contact 22. Connecting the field plate 28 to the source contact 22 provides a reduction in gate-to-drain capacitance (Cgd)
Implementation Method 2
A two-dimensional electron gas (2DEG) 20 arises in the channel layer 16 adjacent the barrier layer 18. A major portion of the electrons in the 2DEG may be attributed to polarization in the AlGaN.
Data Source
AI summary
A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.