Stepped Floating Gate Structure for Flash Memory Erase Path Reduction
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Solution Overview
Problem
Existing flash memory technologies face challenges in achieving high-speed program and erase operations while maintaining memory cell size, process quality, lowering operation voltage, and increasing endurance.
Innovation Solution
A semiconductor structure comprising a substrate, a gate dielectric layer, a floating gate with at least one tip, a first dielectric layer, and a control gate that partially overlaps the floating gate, which reduces the erase path and memory cell size, enhancing process quality and allowing for high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional flash memory structure is used, then the memory cell size is maintained, but the program and erase operation speed is slow
Solution Approach 1:
The floating gate is segmented into multiple portions (first floating gate portion, second floating gate portion, third floating gate portion) with different heights, creating a stepped structure. This segmentation allows for optimized erase paths in different regions, reducing the overall erase path length and enabling faster program and erase operations while maintaining manufacturing precision
Solution Approach 2:
The invention introduces vertical dimensionality by forming floating gates at different heights (first, second, and third floating gate portions with increasing heights). This three-dimensional arrangement reduces the lateral erase path while maintaining storage capacity, thereby improving operation speed without sacrificing manufacturing precision
2Speed
If the memory cell size is reduced, then high-speed operations are enabled, but the erase path between floating gate and control gate increases
Solution Approach 1:
Different regions of the floating gate structure have different heights tailored to local requirements. The first, second, and third floating gate portions have progressively increasing heights, optimizing the local erase path in each region. This local quality variation reduces the overall erase path length while enabling compact memory cell design for high-speed operations
3Manufacturing precision
If the floating gate structure is simplified, then manufacturing process quality is reduced, but the device complexity is lowered
Solution Approach 1:
The floating gate structure employs a dynamic, multi-level configuration with first, second, and third floating gate portions of different heights. This dynamic structure optimizes the electric field distribution during program and erase operations, enhancing process quality. The complexity is managed through systematic formation processes that create the stepped structure in a controlled manner
Data Source
AI summary
The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.