Stepped Gate Dielectric for Power Transistor Dopant Compensation
Solution Overview
Problem
Power transistors with uniform gate dielectric layers face challenges in achieving optimal dopant concentration near the drain region, leading to reduced electrical performance and requiring additional implant operations that increase complexity and yield loss.
Innovation Solution
A stepped gate dielectric layer is implemented, with a thicker portion near the drain region to compensate for locally lower dopant concentration and a thinner portion near the source region, eliminating the need for additional doping sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform thickness gate dielectric layer is used, then the manufacturing process is simple, but the dopant concentration near the drain region is insufficient due to implant scattering
Solution Approach 1:
The gate dielectric layer is designed with non-uniform thickness where the thickness varies across different regions of the gate. Specifically, the dielectric layer is thinner near the drain region and thicker near the source region, allowing local optimization of electrical characteristics without requiring additional doping steps.
Solution Approach 2:
The thickness parameter of the gate dielectric layer is changed from uniform to non-uniform. By controlling the thickness gradient across the gate, the patent achieves better dopant concentration distribution and electrical performance while maintaining a single doping step process.
2Manufacturing precision
If an additional implant operation is performed to increase dopant concentration near the drain region, then the dopant concentration is improved, but the process complexity and yield loss increase
Solution Approach 1:
The gate dielectric layer is pre-formed with a non-uniform thickness profile before the doping step. This preliminary structural preparation ensures that during the subsequent doping process, the dopant atoms are distributed more effectively near the drain region without requiring an additional implant operation, thereby reducing process complexity and yield loss.
3Manufacturing precision
If the gate dielectric layer thickness is increased near the drain region, then the dopant concentration is compensated, but the gate-to-drain capacitance increases
Solution Approach 1:
The gate dielectric layer thickness is locally optimized with a gradient profile that is thinner near the drain region and thicker near the source region. This local quality variation compensates for dopant concentration issues near the drain while minimizing the increase in gate-to-drain capacitance, as the thinner region near the drain reduces the capacitive coupling.
Data Source
AI summary
An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed.