Stepped Gate Electrode Doping for High-Voltage LDMOS Stability
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Solution Overview
Problem
High voltage semiconductor devices, particularly LDMOS transistors, face challenges in achieving stable operation due to variations in breakdown voltages and on-resistance, which affect current drivability and can lead to impurity depletion phenomena, resulting in reduced performance.
Innovation Solution
A high voltage semiconductor device with a gate electrode having a stepped surface profile and a doping profile where the maximum projection range of impurity ions is at the same level across different regions, utilizing a planarized ion implantation buffer layer to ensure uniform doping and prevent impurity depletion, thereby enhancing current drivability and reducing vertical electric field differences between regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate electrode with uniform thickness is used, then the manufacturing process is simple, but impurity depletion occurs in regions with thicker insulation patterns, reducing breakdown voltage and current drivability
Solution Approach 1:
The gate electrode is divided into multiple regions with different thicknesses corresponding to different insulation pattern regions. The first gate electrode region has a first thickness matching the first insulation pattern, while the second gate electrode region has a second thickness matching the thicker second insulation pattern. This segmentation prevents impurity depletion in the thicker region while maintaining manufacturing feasibility through selective epitaxial growth.
Solution Approach 2:
Different regions of the gate electrode are given different local properties (thicknesses) to match the underlying insulation patterns. The thinner first gate electrode region is positioned over the thinner first insulation pattern, while the thicker second gate electrode region is positioned over the thicker second insulation pattern. This local quality variation ensures uniform impurity distribution and prevents depletion phenomena.
2Manufacturing precision
If ion implantation is performed directly on a stepped gate pattern, then the doping process is simple, but the impurity ions do not distribute uniformly, causing maximum projection range differences that reduce device performance
Solution Approach 1:
A planarized ion implantation buffer layer is introduced as an intermediary between the stepped gate pattern and the ion implantation process. This buffer layer has a planar upper surface that serves as a uniform stopping point for ion implantation, ensuring that impurity ions distribute uniformly across different regions. The buffer layer is later removed, having fulfilled its mediating function of achieving precise and uniform doping.
Solution Approach 2:
The ion implantation buffer layer is formed in advance before ion implantation to create a planar surface. This preliminary action ensures that when ions are implanted, they encounter a uniform surface topology, which guarantees uniform distribution and consistent maximum projection ranges across all regions. The buffer layer is then removed after serving its purpose.
3Reliability
If thicker insulation patterns are used to increase breakdown voltage, then voltage handling improves, but the gate electrode requires greater thickness variation that complicates the structure and manufacturing
Solution Approach 1:
The gate electrode is segmented into multiple regions with different thicknesses that correspond to the different insulation pattern thicknesses. The first gate electrode region has a first thickness matching the first insulation pattern thickness, while the second gate electrode region has a second thickness matching the thicker second insulation pattern. This segmentation allows the gate electrode to accommodate varying insulation thicknesses without requiring complex overall structural changes.
Solution Approach 2:
The thickness parameter of the gate electrode is varied locally to match the insulation pattern thicknesses. By changing the gate electrode thickness parameter in different regions (first thickness over first insulation pattern, second thickness over second insulation pattern), the structure accommodates the thicker insulation patterns needed for high breakdown voltage while maintaining manufacturability through controlled epitaxial growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves current drivability and prevents impurity depletion in the gate electrode, leading to more stable and efficient operation of high voltage semiconductor devices by ensuring uniform doping across the device, thus addressing the issues of breakdown voltages and on-resistance.
Implementation Method 1
Impurity ions are implanted into the gate pattern using the planarized ion implantation buffer layer as a screen layer to form a gate electrode
Data Source
AI summary
A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.