Stepped Gate Electrode for FET Parasitic Capacitance
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Solution Overview
Problem
Current field effect transistors face challenges with high parasitic capacitance and silicide roughness due to the geometry of the gate electrode, which affects the reproducibility and reliability of the devices, especially as they are scaled down to smaller sizes.
Innovation Solution
The method involves forming a gate electrode with parallel sidewalls and removing a portion between the sidewall spacers, which reduces parasitic capacitance and prevents silicide penetration, thereby improving the reliability and reproducibility of the transistors by controlling the height and geometry of the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode height is increased to prevent ion penetration and ensure proper sidewall spacer formation, then manufacturing reliability is improved, but parasitic capacitance increases
Solution Approach 1:
The gate electrode is segmented into two distinct height levels: a first height level for the main gate body and a second height level for the gate contacts. This segmentation allows the gate electrode to satisfy multiple requirements simultaneously - the main gate body has sufficient height for reliable ion blocking and spacer formation, while the gate contacts are reduced in height to minimize parasitic capacitance with the interlayer dielectric.
2Productivity
If the gate electrode width is reduced to continue device scaling, then device density is improved, but aspect ratio definition becomes more difficult
Solution Approach 1:
The invention transitions from defining gate electrode dimensions in two dimensions (width and height) to three dimensions by creating a stepped structure. The gate electrode has a first height level for the main body and a second height level for the contacts, allowing independent optimization of width (for density) and height (for manufacturability) without being constrained by aspect ratio limitations.
3Reliability
If metal silicide is formed on the gate electrode to reduce resistance, then electrical conductivity is improved, but silicide roughness and penetration occur
Solution Approach 1:
Metal silicide is applied selectively to different regions of the gate electrode with different thicknesses. The gate contacts at the second height level receive silicide deposition that forms appropriate contact resistance, while the main gate body at the first height level maintains proper electrical characteristics. The reduced height of the gate contacts limits silicide penetration and prevents roughness formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in field effect transistors with reduced parasitic capacitance and minimized silicide roughness, enhancing the reliability and consistency of the devices, even at smaller scales, by effectively managing the gate electrode's height and geometry.
Implementation Method 1
Metal silicide 20 is formed on the gate electrode 12 and the source and drain electrodes 16 to make electrical contact thereto
Implementation Method 2
conductivity-determining ions are implanted into the substrate 14 using the gate electrode 12 as an ion implantation mask to form shallow impurity doped regions or source and drain extensions
Data Source
AI summary
Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.