Stepped Gate Electrode for GaN-on-SiC E-Beam Lithography
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Solution Overview
Problem
High-speed, high-power semiconductor devices face challenges with increased gate and drain leakage currents and reduced breakdown voltage due to shrinking gate lengths and increased electron concentration, which also degrade the unity current gain cutoff frequency (fT) and lead to surface damage and RF current collapse.
Innovation Solution
A stepped field plate gate structure is integrated into the existing e-beam lithography flow, featuring a Schottky gate electrode with lower gate ledges and upper extensions, formed using a patterned multi-layer resist stack to reduce electric fields at the gate edges, stabilize the wafer surface, and enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is shrunk and electron concentration is increased to improve device speed, then device speed is improved, but gate and drain leakage currents increase and breakdown voltage is reduced
Solution Approach 1:
The gate electrode is segmented into multiple portions at different heights (first gate portion at higher elevation, second gate portion at lower elevation), creating a stepped configuration that divides the electric field distribution and reduces peak fields at critical interfaces
Solution Approach 2:
The gate electrode structure transitions from a planar two-dimensional configuration to a three-dimensional stepped structure with varying heights, adding a vertical dimension to control electric field distribution and reduce leakage currents while maintaining high-speed performance
2Reliability
If device features are added to reduce leakage current, then leakage current is reduced, but unity gate current cutoff frequency (fT) is degraded by adding gate capacitance
Solution Approach 1:
Different portions of the gate electrode are positioned at different heights with the first gate portion closer to the channel interface and the second gate portion at a greater distance, creating localized electric field control that reduces leakage without uniformly increasing gate capacitance across the entire gate structure
3Object-affected harmful factors
If gate electrode features are created at edges of deep submicron gates to control fields, then field control is improved, but wafer surface is destabilized and surface damage is induced causing RF current collapse
Solution Approach 1:
The stepped gate electrode configuration is designed in advance to preemptively reduce electric field concentration at the gate-channel interface and edges, cushioning against the formation of surface damage and interface traps before they can occur during device operation
Data Source
AI summary
A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.