Stepped-Gate e-Mode HEMT Structure to Prevent Charge Build-Up
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Solution Overview
Problem
Current enhancement mode (e-mode) high electron mobility transistors (HEMTs) suffer from reliability issues due to gate degradation caused by implant isolation region formation during processing, which leads to charge buildup and potential current paths around the gate.
Innovation Solution
A semiconductor structure with a robust gate design featuring a barrier layer with thicker portions laterally between thinner portions, eliminating the need for implant isolation regions or allowing them to be shallow and offset, thus preventing charge buildup and gate degradation, and including a gate with a semiconductor layer and conductor layer that is narrower in width than the thick semiconductor portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If implant isolation regions are formed during processing, then current paths around the gate are blocked, but gate degradation occurs due to charge build-up
Solution Approach 1:
The barrier layer is segmented into multiple portions with different thicknesses (first barrier portion, second barrier portion, third barrier portion). This segmentation allows different regions to serve different functions: the first barrier portion prevents charge build-up, the second barrier portion blocks current paths, and the third barrier portion provides additional isolation, thereby resolving the contradiction between blocking current paths and preventing gate degradation.
Solution Approach 2:
Different portions of the barrier layer are given different local qualities through varying thicknesses. The first barrier portion has a specific thickness optimized for preventing charge build-up, while the second and third barrier portions have different thicknesses optimized for blocking current paths. This local differentiation allows each region to address specific aspects of the reliability problem without causing harmful effects elsewhere.
2Object-generated harmful factors
If deep implant isolation regions are used to block current paths, then current leakage is reduced, but gate degradation and reliability issues increase
Solution Approach 1:
The barrier layer is divided into multiple segmented portions (first, second, and third barrier portions) with different thicknesses and positions. This segmentation enables the structure to block current leakage paths effectively while distributing the isolation function across multiple regions, preventing the concentration of stress and charge that would lead to gate degradation in a single deep implant region.
Solution Approach 2:
Each barrier portion is locally optimized with specific thickness and positioning. The first barrier portion is positioned and sized to prevent charge build-up, while the second and third portions are configured to block current leakage paths. This local quality differentiation allows current leakage to be blocked without requiring a single deep implant that would cause reliability issues.
3Ease of manufacture
If a uniform barrier layer is used, then manufacturing is simplified, but charge build-up and current paths around the gate cannot be effectively controlled
Solution Approach 1:
The barrier layer is segmented into multiple portions with different thicknesses rather than using a uniform structure. This segmentation can be implemented through selective epitaxial growth or selective removal processes, which are standard semiconductor manufacturing techniques. The segmented structure effectively controls charge build-up and current paths while remaining compatible with existing manufacturing capabilities.
Solution Approach 2:
The barrier layer exhibits local quality variations in the form of different thicknesses in different regions. The first barrier portion has one thickness optimized for charge prevention, while the second and third portions have different thicknesses optimized for current path blocking. These local variations can be manufactured using selective growth or etching processes, balancing manufacturing ease with improved gate performance stability.
Data Source
AI summary
A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer with a thick portion positioned laterally between thin portions and a gate. The gate includes a semiconductor layer (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion positioned laterally between thin portions. The gate also includes a gate conductor layer on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.