Stepped Gate Insulation Mask for LTPS Drain Doping
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Solution Overview
Problem
The existing method for forming a lightly doped drain area in LTPS technology requires two ion doping processes, making it complex and prone to errors in junction depth precision due to mask alignment issues.
Innovation Solution
A method involving the formation of a poly-silicon layer, a gate insulation layer, and a gate metal layer on a substrate, where the gate metal layer is patterned to form a gate electrode, and the gate insulation layer is etched to create a stepped structure with the gate electrode being narrower, allowing for a single ion doping process to form both lightly and heavily doped areas using the stepped structure as a mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two ion doping processes are used to form the lightly doped drain area, then the doping can be completed, but the preparation procedure becomes complex and alignment precision deteriorates
Solution Approach 1:
The patent merges the formation of lightly doped drain area and heavily doped drain area into a single ion doping process. By designing a specific mask structure with different thickness regions, both doping regions are created simultaneously in one step, eliminating the need for two separate doping processes and reducing overall process complexity while maintaining precision.
Solution Approach 2:
The mask structure is segmented into different thickness regions (first thickness region and second thickness region) that correspond to different doping requirements. This segmentation allows different doping doses to be achieved through a single ion doping process by controlling the local mask thickness, thereby avoiding multiple alignment steps.
2Manufacturing precision
If two patterning processes are used for mask alignment, then the lightly doped drain area can be formed, but alignment errors increase and precision deteriorates
Solution Approach 1:
The mask structure is designed and formed in advance with predetermined thickness variations that encode the doping pattern information. This preliminary structuring eliminates the need for subsequent alignment operations during doping, as the pattern is already embedded in the mask geometry before the ion doping process begins.
Solution Approach 2:
The gate insulation layer serves as an intermediary medium that is selectively etched to create the thickness-varied mask structure. This intermediary layer translates the desired doping pattern into physical thickness variations that directly control ion penetration depth, eliminating the need for complex mask alignment procedures.
3Device complexity
If a single ion doping process is used with a stepped structure mask, then process complexity is reduced, but manufacturing precision must be maintained
Solution Approach 1:
The mask structure incorporates local quality variations through different thickness regions. The first thickness region and second thickness region provide different levels of ion blocking, creating locally optimized doping concentrations. This local differentiation allows precise control of doping profiles throughout the structure using a single uniform ion doping process parameter set.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process, improves precision, and allows for flexible adjustment of the doped concentration and size of the lightly doped drain area, effectively alleviating leakage current issues.
Implementation Method 1
doping the poly-silicon layer by a doping process using the gate electrode, and the gate insulation layer with the stepped structure as a mask to form a lightly doped area and a heavily doped area
Data Source
AI summary
Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area.