Stepped Gate Insulator for DMOS Drain Current and Chip Size
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Solution Overview
Problem
Conventional DMOS devices face challenges in driving medium-voltage or high-voltage devices with low voltage gate input due to insufficient drain current, leading to size constraints and instability in channel length modulation, particularly in level shifter blocks.
Innovation Solution
A semiconductor device with a stepped gate insulating layer structure, featuring a thin and thick gate insulating layer combination, and an extended drain junction region that overlaps with the gate electrode, allowing for high drain current and flexible operation as a low-voltage, medium-voltage, or high-voltage device without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If an individual high-voltage device or medium-voltage device with large size is used to convert low voltage to medium voltage or high voltage, then voltage conversion capability is achieved, but drain current is insufficient and chip size increases causing bottleneck phenomenon
Solution Approach 1:
The patent creates a single MOS device structure that can operate as low-voltage, medium-voltage, or high-voltage device by adjusting gate voltage, eliminating the need for separate HV and MV devices. This multi-functionality reduces chip size while maintaining voltage conversion capability across different operating modes.
Solution Approach 2:
The device utilizes changes in gate voltage parameters to switch between different operating modes (LV, MV, HV). By varying the gate voltage, the same physical structure achieves different voltage conversion functions, resolving the contradiction between power capability and chip size.
2Ease of operation
If a low voltage gate input is applied to drive medium-voltage or high-voltage device, then device operation is simplified, but drain current is insufficient and channel length modulation is unstable
Solution Approach 1:
The patent implements dynamic operation where the device adapts its characteristics based on gate voltage input. The same device structure dynamically adjusts its electrical properties to provide stable channel length modulation across different voltage modes, maintaining reliability while keeping operation simple.
Solution Approach 2:
The unified device structure responds to low voltage gate input across all operating modes (LV, MV, HV), providing consistent and stable channel length modulation behavior. This multi-functional design ensures reliability is maintained regardless of the voltage conversion mode being used.
3Power
If finger type MOS device with increased width is used to increase drain current, then current capability is improved, but chip size is reduced causing bottleneck phenomenon
Solution Approach 1:
Instead of increasing device width to improve drain current, the patent changes the operational parameters (gate voltage) to switch between LV, MV, and HV modes. This parameter-based approach increases current capability without requiring additional chip area, avoiding the bottleneck phenomenon.
Solution Approach 2:
A single device structure provides multiple current levels through voltage-mode switching rather than requiring multiple parallel devices or increased width. This universal design achieves high drain current capability while maintaining compact chip size.
Data Source
AI summary
A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.