Stepped Gate Line Layout for Low-Capacitance Fin-Type ICs
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Solution Overview
Problem
As integrated circuit devices are downscaled, they face challenges in maintaining operation accuracy and speed while reducing undesired parasitic capacitance, which is exacerbated by the increasing density of conductive regions in a small area, affecting reliability.
Innovation Solution
The design incorporates a fin-type active region with a gate line featuring a connection protrusion portion and a recess top surface at different vertical levels, along with nanosheet stacks and source/drain contacts, to minimize parasitic capacitance by optimizing the layout and structure of the conductive regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of conductive regions is decreased to reduce parasitic capacitance, then reliability is improved, but the operation speed and accuracy may deteriorate due to downsaling constraints
Solution Approach 1:
The gate line transitions from a conventional planar structure to a three-dimensional structure with a connection protrusion portion extending upward from the substrate. This vertical dimensionality change allows the gate to maintain effective control over the channel while reducing the horizontal footprint of conductive regions, thereby reducing parasitic capacitance without compromising operation speed.
Solution Approach 2:
The gate line is segmented into distinct portions: a connection protrusion portion that extends upward from the substrate and a main gate portion that extends horizontally. This segmentation allows each portion to be optimized independently - the protrusion portion minimizes parasitic capacitance by reducing horizontal area, while the main gate portion maintains effective channel control for proper operation speed.
2Reliability
If the area of conductive regions is decreased to reduce parasitic capacitance, then reliability is improved, but device complexity increases due to the need for multi-level structures
Solution Approach 1:
The gate line utilizes the vertical dimension by extending a connection protrusion portion upward from the substrate. This approach reduces the horizontal area of conductive regions to minimize parasitic capacitance while maintaining functional effectiveness, achieving reliability improvement without requiring complex multi-layer horizontal arrangements.
Solution Approach 2:
The gate line structure exhibits local quality variation: the connection protrusion portion has a different vertical profile (extending upward) compared to the main gate portion (extending horizontally). This localized structural differentiation optimizes each region for its specific function - the protrusion for minimal parasitic capacitance and the main gate for effective channel control - while maintaining overall structural simplicity.
3Productivity
If down-scaling is performed to increase integration density, then productivity is improved, but parasitic capacitance increases due to higher density of conductive regions
Solution Approach 1:
The gate line extends a connection protrusion portion vertically upward from the substrate, transforming part of the conventional horizontal conductive structure into a vertical structure. This dimensionality change reduces the horizontal footprint and density of conductive regions in the plane, thereby reducing parasitic capacitance while maintaining high integration density through efficient space utilization.
Solution Approach 2:
The connection protrusion portion is extracted as a distinct structural element from the conventional planar gate line. By separating this portion and positioning it vertically, the design removes the source of excessive parasitic capacitance (horizontal conductive area) while preserving the essential gate function, thus resolving the harmful effect of parasitic capacitance in downscaled devices.
Data Source
AI summary
An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.