Stepped-Gate LDMOS Layout for Low Rsp and Gate Charge
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Solution Overview
Problem
LDMOS devices face challenges in independently tuning device parameters such as specific resistance (Rsp), gate charge (Qg), and Rsp*Qg product figure of merit, which limits their performance and efficiency in power converter applications, often requiring tradeoffs that negatively affect other parameters like breakdown voltage and safe operating area.
Innovation Solution
The design incorporates a stepped gate architecture with a gate shield, allowing for independent control of Rsp and Qg by adjusting the dimensions of the gate portions and insulator thicknesses, thereby reducing gate-drain capacitance and improving the Rsp*Qg product figure of merit, breakdown voltage, and safe operating area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional LDMOS device design is used, then device parameters such as Rsp, Qg, and Rsp*Qg product are coupled and cannot be independently tuned, but this limits performance and efficiency in power converter applications
Solution Approach 1:
The gate structure is segmented into multiple portions with different gate insulator thicknesses. The first gate portion has a first gate insulator thickness while the second gate portion has a second gate insulator thickness, allowing independent control of electrical characteristics in different regions of the device
Solution Approach 2:
Different regions of the gate structure are assigned different insulator thicknesses to achieve local optimization. The thinner gate insulator under the first gate portion provides lower resistance while the thicker gate insulator under the second gate portion reduces gate-drain capacitance, enabling simultaneous optimization of multiple parameters
2Reliability
If gate dimensions are reduced to lower Rsp and Qg, then Rsp*Qg product improves, but breakdown voltage and safe operating area are adversely affected
Solution Approach 1:
The gate is divided into multiple portions that can be independently optimized. The first gate portion is optimized for low resistance with thinner insulator, while the second gate portion extends over the drift region with thicker insulator to maintain breakdown voltage
Solution Approach 2:
The gate structure extends in multiple dimensions with different insulator thicknesses at different locations. This dimensional variation allows the device to achieve low Rsp*Qg product while maintaining high breakdown voltage by distributing the functional requirements across different spatial regions
3Productivity
If switching frequency is increased to improve power conversion efficiency, then power loss increases due to higher gate charge requirements
Solution Approach 1:
The gate insulator thickness parameter is varied across different regions of the gate structure. This parameter change enables optimization of the Rsp*Qg product figure of merit, allowing higher switching frequencies with reduced power loss
Data Source
AI summary
An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm2, a gate charge (Qg) of about 1.9-2.0 nC/mm2, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.