Stepped Gate Stack Structure for Lower Leakage in Multi-Gate Transistors
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Solution Overview
Problem
Existing multi-gate semiconductor devices, such as FinFETs and GAA transistors, face challenges in reducing parasitic capacitance and leakage current, which affect their performance and efficiency.
Innovation Solution
A method is introduced that involves forming a funnel-shaped trench by recessing the gate stack and gate spacers, depositing dielectric spacers to partially fill the trench, and forming a metal cap over the gate stack, which is laterally confined by the dielectric spacers, thereby reducing the distance between the metal cap and neighboring source/drain contacts, leading to reduced parasitic capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate stack and gate spacers are recessed to form a funnel-shaped trench and dielectric spacers are deposited to partially fill it, then the distance between the metal cap and neighboring source/drain contacts is reduced, but the device structure becomes more complex
Solution Approach 1:
The gate stack structure is segmented into multiple portions with different heights, creating a stepped configuration. The first gate stack portion has a first height and the second gate stack portion has a second height different from the first height. This segmentation allows the metal cap to be positioned at optimal distances from different source/drain contacts, reducing parasitic capacitance while maintaining manufacturability through controlled sequential deposition processes.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional stepped structure by varying the height of different gate stack portions. This dimensional change enables the metal cap to achieve reduced distance to source/drain contacts in the vertical dimension, effectively reducing parasitic capacitance without requiring excessive lateral complexity in the fabrication process.
2Reliability
If multi-gate devices are used to improve gate control, then off-state current is reduced, but parasitic capacitance and leakage current remain problematic
Solution Approach 1:
The invention applies local quality by creating different height portions of the gate stack at specific locations. The first and second gate stack portions have different heights tailored to their respective positions, allowing optimized control over local electric fields and charge distribution. This local differentiation reduces parasitic capacitance and leakage current at critical interfaces while preserving the overall multi-gate control mechanism.
Solution Approach 2:
The invention changes the geometric parameter of the gate stack by introducing varying heights across different portions. This parameter change modifies the electrical characteristics, reducing parasitic capacitance and leakage current. The stepped configuration alters the electric field distribution and charge storage properties, effectively mitigating harmful effects while maintaining the benefits of multi-gate control.
Data Source
AI summary
Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece having a channel region, a gate structure over the channel region, gate spacers extending along sidewalls of the gate structure, and an etch stop layer extending along sidewalls of the gate spacers. The method also includes performing an etching process to recess the gate spacers and the gate structure, thereby forming a funnel-shaped trench, depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench, etching back the dielectric layer to form dielectric spacers on the recessed gate spacers, forming a metal cap on the gate structure without forming the metal cap on the recessed gate spacers, and forming a dielectric cap on the metal cap.