Stepped Gate Spacer Structure for Low-Capacitance Contacts
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes, as the scaling-down process complicates fabrication processes and increases the complexity of integrated circuits.
Innovation Solution
The method involves forming an interlayer dielectric layer and a gate stack on a semiconductor substrate, followed by the creation of air spacers and spacers to surround the gate stack. A second spacer is formed on the first spacer and the air spacer, with a portion in contact with the sidewall of the first spacer. A contact hole is formed to land on the second spacer and the gate stack, with the sidewall of the contact hole defined by the second spacer. This process helps in reducing parasitic capacitance and enhancing the performance of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the geometric size of semiconductor devices is decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple sequential steps including forming first spacers, forming air spacers, forming second spacers, and forming contact holes. Each step creates progressively smaller features while maintaining control through staged processing rather than attempting to create all features in a single step.
Solution Approach 2:
The patent introduces vertical spacer structures that extend above the gate stack to define contact hole sidewalls. This vertical dimension provides mechanical support and dimensional control that enables precise formation of smaller horizontal features without increasing overall process complexity.
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area is reduced, but reliability of semiconductor devices becomes more difficult to maintain
Solution Approach 1:
Air spacers are formed between the gate stack and surrounding structures to create physical separation that reduces parasitic capacitance. This pre-established isolation protects against electrical interference and maintains signal integrity even as device dimensions shrink and features are placed closer together.
Solution Approach 2:
The second spacer acts as an intermediary structure that defines the sidewall of contact holes and provides a controlled interface between conductive features and insulating materials. This intermediate layer ensures reliable electrical connections while maintaining proper spacing to prevent short circuits.
3Reliability
If parasitic capacitance between gate stacks and bottom conductive features is reduced, then device performance is improved, but additional spacer structures increase fabrication complexity
Solution Approach 1:
The air spacer structure serves multiple functions: it provides electrical isolation to reduce parasitic capacitance, defines dimensional boundaries for subsequent processing steps, and maintains mechanical support for overlying structures. This multi-functionality reduces the need for additional dedicated isolation structures.
Solution Approach 2:
The patent changes the material parameter from solid dielectric material to air (vacuum) for the spacer region. This parameter change dramatically reduces parasitic capacitance while the air spacer can be formed through simple etching processes that remove material rather than depositing complex multi-layer dielectric structures.
Data Source
AI summary
A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.