Stepped Gate Spacers Using Helmet Layer Etch Protection
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits increases manufacturing complexity, requiring advanced processing techniques to maintain efficiency and reduce costs, particularly in the formation of FinFET devices where existing methods may cause unwanted damage to dummy gate stacks, semiconductor fins, and isolation structures during the fin sidewall pull back process.
Innovation Solution
A method involving the formation of a helmet layer over dummy gate stacks, semiconductor fins, and isolation structures, which is selectively etched to protect these components during the fin sidewall pull back process, allowing for the formation of gate spacers with stepped sidewalls and subsequent epitaxial growth of source/drain structures, thereby reducing height loss and preventing unwanted damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the fin sidewall pull back process is performed without protective measures, then the manufacturing process can be simplified, but unwanted damage occurs to dummy gate stacks, semiconductor fins, and isolation structures
Solution Approach 1:
A helmet layer is introduced as an intermediary protective structure that lines the sidewalls of dummy gate stacks, semiconductor fins, and isolation structures. This helmet layer acts as a mediator that prevents direct contact between the fin sidewall pull back process and the vulnerable components, thereby preventing damage while allowing the process to proceed.
Solution Approach 2:
The helmet layer is formed in advance before the fin sidewall pull back process. By performing this protective action preliminarily, the vulnerable components are pre-protected against the harmful effects that will occur during the subsequent pull back process, eliminating the need for complex protective measures during the actual process.
2Manufacturing precision
If advanced processing techniques are implemented to protect components during scaling down, then manufacturing precision and component protection are improved, but manufacturing complexity increases
Solution Approach 1:
The protective structure is segmented into distinct components: a helmet layer that lines specific sidewalls and a gate spacer that forms on exposed sidewalls. This segmentation allows each component to perform its specific function independently, providing precise protection where needed while maintaining simplicity in other areas.
Solution Approach 2:
The helmet layer is selectively formed only on the sidewalls of dummy gate stacks, semiconductor fins, and isolation structures that require protection. This local application of the protective layer provides precise protection exactly where needed, avoiding unnecessary complexity in areas where protection is not required.
3Object-affected harmful factors
If the helmet layer completely covers all sidewalls for maximum protection, then component protection is maximized, but the formation of gate spacers with stepped sidewalls becomes impossible
Solution Approach 1:
Vertical portions of the helmet layer are selectively removed from the sidewalls where gate spacers need to form. By extracting the helmet layer material from specific locations, the underlying sidewalls are exposed to allow gate spacer formation, while the helmet layer remains on other sidewalls to provide continued protection.
Solution Approach 2:
The helmet layer is partially removed rather than completely removed, applying the protective action only where needed. This partial action allows the process to achieve both protection (where the helmet layer remains) and gate spacer formation (where the helmet layer is removed), avoiding the need for complete removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the height loss of dummy gate stacks, semiconductor fins, and isolation structures, enhancing the manufacturing efficiency and device performance by preventing damage during the fin sidewall pull back process and enabling improved carrier mobility through strained channels.
Implementation Method 1
etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure
Implementation Method 2
forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer
Implementation Method 3
etching the spacer layer and the remaining helmet layer to form gate spacers on opposite sidewalls of the gate structure, wherein each of the gate spacers has a stepped sidewall
Implementation Method 4
forming source/drain epitaxy structures over the semiconductor fin and on opposite sides of the gate structure
Data Source
AI summary
A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.