Stepped Gate Insulation in Power MOSFETs for UIS Stability
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Solution Overview
Problem
Power semiconductor devices with stepped gate insulating layers face a technical contradiction where improved switching loss characteristics lead to deteriorated UIS characteristics, resulting in rapid voltage and current spikes that can destroy the device.
Innovation Solution
A power semiconductor device design featuring a substrate with a first conductivity type epitaxial layer, a second conductivity type well, a second conductivity type ion implantation region, a source region, a gate insulating layer with a channel and protruding gate insulating layers, and a source electrode, where the ion implantation region has a higher lateral resistance concentration than the well, improving UIS characteristics by reducing Miller Capacitance and internal base resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a stepped gate insulating layer structure is adopted to reduce oxide capacitance and improve switching loss characteristics, then switching loss is reduced, but UIS characteristics deteriorate due to increased di/dt change amount and rapid voltage and current spikes
Solution Approach 1:
The patent applies local quality by creating different regions with different insulating layer thicknesses: a first insulating layer region with thickness T1 over the P-well, and a second insulating layer region with thickness T2 over the N+ region, where T1 < T2. This local differentiation allows the gate insulating layer to provide both low capacitance (over the P-well) and stable UIS characteristics (over the N+ region), resolving the technical contradiction between switching loss reduction and UIS reliability.
2Speed
If the gate insulating layer thickness is reduced to lower oxide capacitance Cgd, then switching speed increases and switching loss decreases, but the parasitic bipolar device becomes more prone to operate under UIS condition
Solution Approach 1:
The patent implements local quality by varying the gate insulating layer thickness across different regions: a thinner first insulating layer (T1) over the P-well region to reduce capacitance and improve switching speed, and a thicker second insulating layer (T2) over the N+ region to suppress parasitic bipolar operation during UIS conditions. This spatial differentiation of insulating layer thickness simultaneously achieves both objectives.
Solution Approach 2:
The patent applies preliminary action by pre-forming the stepped gate insulating layer structure during manufacturing, with the thicker second insulating layer region prepared in advance over the N+ region. This preliminary structural preparation ensures that when UIS conditions occur, the parasitic bipolar device is already protected by the thicker insulation, preventing harmful operations before they can occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces switching loss and improves UIS characteristics by lowering the internal base resistance and Miller Capacitance, preventing device destruction from voltage and current spikes.
Implementation Method 1
a second conductivity type ion implantation region partially disposed in the second conductivity type well
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A power semiconductor device includes a substrate, a first conductivity type epitaxial layer disposed on the substrate, a second conductivity type well partially disposed on the first conductivity type epitaxial layer, a second conductivity type ion implantation region partially disposed in the second conductivity type well, a source region partially disposed in the second conductivity type well and disposed on the second conductivity type ion implantation region, a gate insulating layer disposed on the source region and the second conductive type well, a gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate, and a source electrode disposed on the source region. The gate insulating layer may include a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness thicker than the first thickness, A concentration in a Rb region which is a lateral resistance of the second conductivity type ion implantation region may be higher than that of the second conductivity type well.