Stepped Gate Wiring Structure for Display Short Circuit Prevention
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Solution Overview
Problem
High-resolution display apparatuses face an increased risk of short circuits between adjacent wirings due to reduced pixel sizes and higher pixel density, leading to higher defective product rates.
Innovation Solution
A display apparatus design featuring a substrate with semiconductor layers, gate insulating layers, and wirings, including a short circuit protection area with increased intervals between gate wirings and a stepped part to prevent short circuits, where the stepped part protrudes from one gate wiring to be disposed under or on another, forming a step on the insulating layer to reduce valley formation and wiring proximity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pixel size is reduced and pixel density is increased to achieve high resolution, then the display resolution is improved, but the distance between adjacent transistors and wirings is reduced leading to increased short circuit risk
Solution Approach 1:
The patent applies local quality by creating a stepped part only in specific critical areas where short circuits are most likely to occur, rather than uniformly increasing intervals everywhere. The stepped part is formed between gate wirings in regions where pixel density is highest and spacing is most critical, thereby locally enhancing reliability without compromising overall display resolution.
Solution Approach 2:
The patent introduces a vertical dimension by forming a stepped part that protrudes from one gate wiring toward another, creating a three-dimensional structure. This vertical protrusion increases the effective spacing between adjacent wirings in the critical region, adding a new dimensional approach to preventing short circuits while maintaining planar layout efficiency.
2Reliability
If the interval between gate wirings is increased in critical areas to prevent short circuits, then the reliability is improved, but the area occupied by the wiring structure increases
Solution Approach 1:
The stepped part is formed only in specific critical areas where short circuits are most likely to occur, such as between gate wirings in high-density pixel regions. This localized approach increases spacing only where necessary, avoiding unnecessary area expansion in regions where the standard wiring layout is sufficient.
Solution Approach 2:
The stepped part is formed by utilizing the existing gate wiring structure and insulating layers, nesting the protective feature within the existing wiring architecture. The stepped part protrudes from one gate wiring and is covered by subsequent insulating layers, effectively using the existing structural elements to create the protective feature without adding separate external components.
3Reliability
If a stepped part is formed to prevent short circuits, then the reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The stepped part is formed by utilizing the existing gate wiring structure and insulating layers, nesting the protective feature within the existing wiring architecture. The stepped part protrudes from one gate wiring and is covered by subsequent insulating layers, effectively using the existing structural elements to create the protective feature without adding separate external components.
Solution Approach 2:
The stepped part is formed during the gate wiring formation process itself, before subsequent insulating layers are deposited. This preliminary formation of the stepped structure allows it to be integrated into the existing manufacturing flow, and the subsequent insulating layers automatically cover and protect the stepped part as they are deposited over the entire surface.
Data Source
AI summary
Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.