Stepped Gate Wiring Structure for Display Short Circuit Prevention
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Solution Overview
Problem
High-resolution display apparatuses face an increased risk of short circuits between adjacent wirings due to reduced distances between transistors, leading to higher defective product rates.
Innovation Solution
A display apparatus design featuring a substrate with semiconductor layers, gate insulating layers, and wirings, including a short circuit protection area with increased intervals between gate wirings and a stepped part to prevent short circuits, formed on the third gate insulating layer to reduce the occurrence of valleys and potential short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the distance between adjacent transistors is reduced to increase pixel density, then the resolution is improved, but the risk of short circuits between wirings increases
Solution Approach 1:
The patent applies local quality by creating a stepped part only in specific critical areas where short circuits are most likely to occur, rather than uniformly increasing intervals everywhere. The stepped part is formed at locations where gate wirings intersect with data lines or driving voltage lines, providing enhanced protection precisely where needed while maintaining tight spacing in non-critical areas.
Solution Approach 2:
The patent resolves the wiring short circuit issue by transitioning from a two-dimensional planar layout to a three-dimensional stepped structure. The stepped part extends vertically from the gate insulating layer, creating additional spatial separation between adjacent wirings in the vertical dimension while maintaining horizontal spacing constraints for high resolution.
2Reliability
If the interval between gate wirings is increased in short circuit protection areas, then short circuit risk is reduced, but the area occupied by the display apparatus increases
Solution Approach 1:
The stepped part is implemented only in localized short circuit protection areas where gate wirings intersect with data lines or driving voltage lines, rather than uniformly across the entire display. This localized approach provides enhanced short circuit protection precisely where needed while minimizing the overall area impact.
Solution Approach 2:
By extending the gate wiring structure vertically to form a stepped part, the patent achieves additional wiring separation in the vertical dimension without proportionally increasing the horizontal footprint, thus protecting against short circuits while maintaining compact display area.
3Reliability
If a stepped part is formed on the gate insulating layer, then valley formation is prevented and short circuit risk is reduced, but the manufacturing complexity increases
Solution Approach 1:
The stepped part is formed only in specific short circuit protection areas rather than across the entire gate insulating layer, providing valley prevention and short circuit protection locally where critical intersections occur, while keeping the overall structure simpler in non-critical regions.
Solution Approach 2:
The gate insulating layer is segmented into different height levels, with stepped parts formed only in critical protection areas. This segmentation approach prevents valleys and short circuits where needed while avoiding unnecessary structural complexity in areas where protection is not required.
Data Source
AI summary
Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.