Stepped Housing IC Package for High-Density Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing density of integrated circuits requires more electrical connections, leading to larger chip packages that occupy more space on printed circuit boards, resulting in higher system costs due to the need for more boards.
Innovation Solution
A chip package design with a housing featuring stepped surfaces and conductors on each surface, allowing for reduced spacing between housing pads while maintaining compliance with design rules, enabling connections to higher density integrated circuits without increasing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of traces or conductors is increased to accommodate higher density integrated circuits, then the number of electrical connections is improved, but the chip package size increases
Solution Approach 1:
The patent transitions from a single-plane conductor layout to a multi-layer three-dimensional structure. Conductors are distributed across multiple layers (first layer, second layer, third layer) with vertical interconnections via vias. This dimensional expansion allows N electrical connections to be achieved in a compact footprint by utilizing the vertical dimension, resolving the contradiction between increasing connection density and maintaining package size.
Solution Approach 2:
The conductor layer is segmented into multiple distinct layers (first layer with first conductors, second layer with second conductors, third layer with third conductors). Each layer handles a subset of the total electrical connections, allowing the overall connection density to increase without proportionally increasing the area of any single layer. This segmentation enables efficient spatial distribution of conductors.
2Manufacturing precision
If traces are spaced according to fabrication design rules, then manufacturing precision is maintained, but the chip package size increases to accommodate the spacing
Solution Approach 1:
By distributing conductors across multiple vertical layers, the patent reduces the horizontal spacing requirements on any single layer. The vertical separation between layers provides additional design space, allowing each layer to maintain proper trace spacing for manufacturing precision while the overall package remains compact due to the efficient use of the vertical dimension.
Solution Approach 2:
Segmenting the conductor layout into multiple layers allows each layer to independently satisfy fabrication design rules for trace spacing. The via connections between layers provide vertical interconnection without requiring additional horizontal space, enabling compliance with manufacturing precision requirements while minimizing the overall chip package area.
3Quantity of substance
If more bonding pads are incorporated into integrated circuits to increase device density, then the number of electrical contacts is improved, but the spacing between contacts decreases
Solution Approach 1:
The patent utilizes multiple vertical layers to accommodate a high number of bonding pads and their corresponding conductors. By distributing contacts and conductors across different layers (first layer, second layer, third layer), the spacing between adjacent contacts on any single layer can be maintained at acceptable levels while the total number of contacts is significantly increased through the vertical dimension.
Solution Approach 2:
The bonding pads and conductors are segmented into different layers, with each layer containing a subset of the total contacts. This segmentation allows the spacing between contacts on each individual layer to be optimized for manufacturing and signal integrity, while the overall system achieves high contact density through the multi-layer arrangement connected by vias.
Data Source
AI summary
Consistent with the present disclosure, a package is provided that includes a housing having a recessed portion to accommodate an integrated circuit or chip. The housing has an inner periphery that defines or delineates the recessed portion. The inner periphery may be stepped and includes first and second surfaces that are spaced vertically from one another and extend in respective parallel planes, for example, to thereby constitute first and second shelves. First bonding pads or contacts (“housing pads”) may be provided on the first surface, which may electrically connect or interconnect with first pads on the integrated circuit (“IC pads”), and second housing pads may be provided on the second surface, which can electrically connect or interconnect with second IC pads. Thus, the IC pads connect to corresponding housing pads on the inner periphery of the housing that are above and below one another. Since the housing pads are not provided on the same surface, the number of housing pads on each step or shelf of the periphery can be reduced, and the housing pads can be spaced from one another by a spacing or pitch that is greater than that of the IC pads. Accordingly, the dimensions and spacing of the housing pads may comply with relevant design rules, while providing connection to an increased number of IC pads.