Stepped Image Sensor Package for Low-Profile Reliability
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Solution Overview
Problem
Current packaging techniques for image sensor chips, such as chip-on-board and shellcase wafer level CSP, face challenges with assembly limitations, size constraints, yield issues, and high costs due to packaging of untested chips, particularly for higher pixel image sensors, which demand a more reliable and cost-effective low-profile solution.
Innovation Solution
A wafer-level low-stress package solution involving a crystalline handler with a cavity and stepped sidewalls, where the sensor chip is mounted to a stepped surface, and conductive material is used to provide electrical connectivity, with a cover that seals the package while allowing light transmission, enabling separate testing and encapsulation of chips for reduced defects and improved mechanical and electrical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip-on-board or shellcase wafer level CSP packaging is used for higher pixel image sensors, then electrical connectivity and mechanical support are provided, but assembly becomes increasingly difficult, package size increases, and yield problems occur due to packaging of defective chips
Solution Approach 1:
The patent implements preliminary testing of individual sensor chips before packaging by mounting them on a wafer-level substrate with test circuits. This allows defective chips to be identified and excluded before final packaging, resolving the contradiction by enabling reliability verification without requiring complex post-packaging testing procedures
2Productivity
If shellcase wafer level CSP packaging is used, then wafer-level processing efficiency is achieved, but defective chips are packaged before testing which drives up cost
Solution Approach 1:
The patent performs preliminary electrical testing of sensor chips at the wafer level before singulation and final packaging. Test circuits are integrated into the wafer-level substrate to enable functional verification of each chip, allowing defective chips to be identified and excluded early in the process, thus maintaining high productivity while reducing waste of defective components
Solution Approach 2:
The wafer-level substrate provides self-testing capability through integrated test circuits that automatically verify the functionality of mounted sensor chips. This self-service approach enables quality control without requiring external testing equipment, maintaining packaging efficiency while eliminating waste from defective chip packaging
3Manufacturing precision
If higher pixel image sensors are used, then image quality improves, but assembly limitations and size constraints make packaging increasingly difficult
Solution Approach 1:
The patent segments the packaging process into distinct stages: wafer-level mounting and testing, followed by individual chip packaging. This segmentation allows high-precision sensor chips to be handled and tested in a controlled wafer-level environment, reducing the complexity of assembling individual high-pixel-density chips and improving ease of operation
Solution Approach 2:
The wafer-level substrate serves as an intermediary platform that facilitates the packaging of high-pixel-density sensor chips. It provides a stable mounting surface with integrated test circuits, enabling verification of chip functionality before final packaging, thus simplifying the overall assembly process for high-precision sensors
4Length of stationary object
If a low-profile packaging solution is implemented, then device size is reduced, but mechanical support and electrical connectivity may be compromised
Solution Approach 1:
The patent transitions from traditional vertical packaging structures to a wafer-level planar mounting approach. Sensor chips are mounted flat on the substrate surface with electrical connections made in the plane of the substrate, reducing the vertical profile height while maintaining adequate mechanical support and electrical connectivity through the distributed substrate structure
Data Source
AI summary
An image sensor package includes a crystalline handler having opposing first and second surfaces, and a cavity formed into the first surface. At least one step extends from a sidewall of the cavity, wherein the cavity terminates in an aperture at the second surface. A cover is mounted to the second surface and extends over and covers the aperture. The cover is optically transparent to at least one range of light wavelengths. A sensor chip is disposed in the cavity and mounted to the at least one step. The sensor chip includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors.