Stepped Insulating-Layer Transistor for Uniform Large-Area Displays
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Solution Overview
Problem
Existing display technologies face challenges in achieving high performance and integration density using oxide semiconductors due to increased process costs and difficulty in maintaining uniform characteristics when depositing the semiconductor layer across large areas, leading to reduced driving current and potential defects like mura in display panels.
Innovation Solution
A transistor design with a semiconductor layer disposed conformally over a first insulating layer having varying thicknesses, creating multiple channel areas, allowing for parallel connection of source and drain electrodes, thereby increasing driving current without increasing area, and utilizing an oxide semiconductor material like indium-gallium-zinc-oxide (IGZO) for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the semiconductor layer is deposited across large areas, then the display area is increased, but the uniformity of characteristics deteriorates
Solution Approach 1:
The first insulating layer is divided into multiple regions with different thicknesses (first region, second region, third region), which segments the deposition process into controlled zones. This segmentation allows the semiconductor layer to be formed with precise thickness control in each region, maintaining uniform characteristics even across large display areas.
Solution Approach 2:
Different regions of the first insulating layer are given different thicknesses according to local requirements. The gate electrode is positioned in the first region with greater thickness, while source and drain electrodes are positioned in regions with different thicknesses. This local quality approach ensures optimal electrical characteristics in each specific location of the transistor.
2Area of stationary object
If the oxide semiconductor is deposited across large areas, then the display area is increased, but the process cost increases
Solution Approach 1:
By segmenting the first insulating layer into multiple thickness regions, the patent enables precise control of the oxide semiconductor deposition process. This segmentation approach improves manufacturing precision and reduces defects, thereby lowering overall process costs even when producing large-area displays.
Solution Approach 2:
The patent utilizes parameter changes in the thickness of the first insulating layer across different regions to optimize the deposition process. By adjusting the thickness parameter locally, the patent achieves uniform oxide semiconductor characteristics without requiring excessive deposition time or material, thus reducing process costs.
3Power
If the transistor area is increased, then the driving current is improved, but the integration density deteriorates
Solution Approach 1:
The patent transitions from a planar transistor design to a three-dimensional structure by forming the semiconductor layer with different thicknesses in the vertical dimension. The first insulating layer has varying thicknesses (first, second, and third regions), creating a multi-level structure that increases the effective channel area without increasing the footprint, thereby improving integration density while maintaining high driving current.
Solution Approach 2:
Different regions of the transistor are given different local qualities in terms of insulating layer thickness. The gate electrode region has greater thickness than the source and drain regions, creating localized electrical characteristics that optimize current flow while maintaining a compact overall structure, thus improving integration density.
4Power
If the insulating layer thickness is increased, then the transistor performance is improved, but the conformal deposition becomes more difficult
Solution Approach 1:
The insulating layer is segmented into multiple regions with different thicknesses, which simplifies the conformal deposition process. Instead of attempting to deposit a uniformly thick layer across the entire structure, the patent divides the structure into discrete thickness regions, making it easier to achieve conformal coverage of the gate and source/drain electrodes while maintaining optimal transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances current density and reduces production energy by optimizing the transistor's performance within the same area, preventing defects like mura in display panels while maintaining high integration density and efficiency.
Implementation Method 1
the semiconductor layer is disposed on the upper surface of the first insulating layer having the at least one step in a conformal manner
Data Source
AI summary
A transistor and a display apparatus including the transistor are discussed. The transistor can include a substrate, a gate electrode disposed on the substrate, a first insulating layer disposed on the gate electrode, and a semiconductor layer disposed on the first insulating layer so as to overlap the gate electrode in a vertical direction. An upper surface of the first insulating layer includes at least one step.