Stepped Interconnect Structure for Plasma-Damage-Resistant Etching
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Solution Overview
Problem
Existing anisotropic etch processes used in semiconductor manufacturing often cause plasma damage to underlying metal interconnect structures and semiconductor devices, leading to electrical failures and performance degradation.
Innovation Solution
The implementation of stepped metal interconnect structures, where only the metallic compound material portions are exposed during the formation of openings through a dielectric material layer, reduces plasma damage by using a metallic barrier liner with high resistivity to prevent excessive electrical current flow and oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an anisotropic etch process is used to pattern openings through an overlying insulating layer, then the etching precision and anisotropy are improved, but plasma damage to underlying metal interconnect structures and semiconductor devices increases
Solution Approach 1:
A metallic compound material layer (such as tantalum nitride or tungsten silicide) is introduced as an intermediary barrier between the metal interconnect structure and the underlying semiconductor devices. This intermediate layer has high electrical resistivity and serves as a plasma damage barrier during anisotropic etching, preventing direct plasma exposure to the metal interconnect structure while allowing the etch process to proceed with high precision through the overlying insulating layer.
Solution Approach 2:
The electrical resistivity parameter of the barrier structure is increased by using metallic compound materials with inherently higher resistivity compared to pure metals. This parameter change reduces the antenna effect and limits excessive electrical current flow during plasma processing, thereby reducing plasma damage to underlying structures while maintaining the etching precision benefits of the anisotropic etch process.
2Object-affected harmful factors
If a metallic barrier liner with high resistivity is used to reduce plasma damage, then plasma-induced damage is reduced, but the device complexity increases
Solution Approach 1:
The barrier structure is segmented into distinct functional layers: a metallic compound material layer specifically positioned to protect against plasma damage, separate from the conductive metal interconnect material. This segmentation allows each layer to perform its specific function optimally—the metallic compound layer provides plasma protection and current limitation, while the metal interconnect layer provides electrical connectivity—without requiring complete redesign of the entire interconnect system.
Solution Approach 2:
The interconnect structure uses composite material construction, combining metallic compound materials (such as tantalum nitride or tungsten silicide) with conventional metal interconnect materials. This composite approach leverages the high resistivity and plasma resistance properties of the metallic compound while maintaining the excellent electrical conductivity of the metal interconnect material, achieving plasma damage reduction without sacrificing electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces plasma-induced damage to semiconductor devices and metal interconnect structures, enhancing the reliability and performance of the underlying electrically connected devices.
Implementation Method 1
previously formed metal interconnect structures may suffer undesirable plasma damage during an anisotropic etch process
Implementation Method 2
metallic barrier liner with high resistivity to prevent excessive electrical current flow and oxidation
Implementation Method 3
metallic barrier liner with high resistivity to prevent excessive electrical current flow
Data Source
AI summary
A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.