Stepped Interconnect Structure for Stacked Semiconductor Dies
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving smaller die sizes with higher density and finer interconnect pitches due to the thickness of stacked semiconductor dies, which results in large bumps that restrict input/output count and are susceptible to collapse, leading to electrical shorts and device defects.
Innovation Solution
A method of forming a stepped interconnect structure over a semiconductor die, allowing for smaller bumps and finer interconnect pitches by using conductive pillars and multiple layers to connect stacked semiconductor dies, reducing the thickness of the package and increasing the input/output count while minimizing bump collapse risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional interconnect structures are used with thick semiconductor dies stacked, then the package can be assembled, but the bumps become large which restricts interconnect pitch and reduces I/O count
Solution Approach 1:
The interconnect structure is segmented into multiple layers with different functions: lower interconnect layers provide mechanical support and carry some signals, while upper interconnect layers provide additional I/O connections. This segmentation allows bumps to be smaller since not all I/O need to pass through thick bumps, thereby increasing interconnect pitch and I/O count
Solution Approach 2:
The solution transitions from a single-layer interconnect structure to a multi-layer three-dimensional interconnect architecture. By adding vertical dimensionality with multiple interconnect layers at different heights, the patent enables more I/O connections without increasing bump size, as signals can be distributed across multiple layers rather than requiring larger individual bumps
2Reliability
If traditional interconnect structures are used with thick semiconductor dies stacked, then the package can be assembled, but the large bumps are susceptible to collapse causing electrical shorts and device defects
Solution Approach 1:
The mechanical support function is segmented from the electrical interconnect function. Lower interconnect layers provide mechanical support and structural stability, while upper interconnect layers provide additional electrical connections. This allows the use of smaller, more reliable bumps that are less susceptible to collapse
Solution Approach 2:
The lower interconnect layers act as intermediary structures that provide mechanical support and distribute loads. This intermediary support structure reduces the stress on individual bumps, preventing collapse and electrical shorts while enabling smaller bump dimensions for improved reliability
3Area of stationary object
If die size is reduced to achieve smaller footprint, then device size decreases, but the thickness of stacked dies remains the same requiring larger bumps
Solution Approach 1:
By transitioning to a multi-layer interconnect structure, the patent adds vertical dimensionality that enables more I/O connections without increasing horizontal bump size. This allows smaller die with smaller footprints while maintaining adequate I/O count through the use of multiple interconnect layers at different heights
Solution Approach 2:
The interconnect function is segmented across multiple layers, allowing smaller bumps to be used since the total I/O capacity is distributed across multiple layers rather than requiring large individual bumps. This enables smaller die size and footprint while maintaining connectivity requirements
Data Source
AI summary
A semiconductor device comprises a first semiconductor die. An encapsulant is disposed around the first semiconductor die. A first stepped interconnect structure is disposed over a first surface of the encapsulant. An opening is formed in the first stepped interconnect structure. The opening in the first stepped interconnect structure is over the first semiconductor die. A second semiconductor die is disposed in the opening of the first stepped interconnect structure. A second stepped interconnect structure is disposed over the first stepped interconnect structure. A conductive pillar is formed through the encapsulant.