Stepped Interposer Module for Stacked Chip Package Power Delivery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Miniaturization of stacked chip packages faces challenges in accommodating decoupling technology without increasing form factor or product cost, as high-density metal-insulator-metal (MIM) capacitance is costly and complex, and package capacitors are prohibited in small form-factor devices, leading to design complexity and performance trade-offs.
Innovation Solution
The introduction of a stepped interposer module frame within the chip package, featuring two steps of different heights with frame vias and lateral routing, allows for improved power delivery and signal transmission without increasing package size or cost, by positioning electronic components on the interposer module instead of the package substrate, reducing the need for additional capacitors and minimizing silicon wafer fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density metal-insulator-metal (MIM) capacitance is used for decoupling, then power delivery noise mitigation is improved, but product cost and manufacturing complexity increase
Solution Approach 1:
The patent introduces an interposer module as an intermediary component between the package substrate and the chip. This interposer integrates decoupling capacitors and power delivery network elements, serving as a mediator that provides noise mitigation functionality without requiring complex high-density MIM capacitor implementations on the substrate itself. The interposer simplifies the overall manufacturing process while maintaining power delivery performance.
2Reliability
If package capacitors are added for power delivery noise mitigation, then reliability is improved, but form factor increases
Solution Approach 1:
The patent utilizes the vertical dimension by implementing decoupling capacitors in the Z-direction (vertical stacking) rather than only in the planar XY-plane. The interposer module stacks capacitors vertically above the power delivery network, enabling noise mitigation functionality without increasing the lateral footprint of the package. This three-dimensional integration allows compact form factor while maintaining reliability.
3Volume of moving object
If decoupling technology is accommodated in miniaturized packages, then device size is reduced, but design complexity and performance trade-offs increase
Solution Approach 1:
The patent merges multiple functions into the interposer module: it combines the substrate mounting function, the power delivery network, the decoupling capacitor integration, and the signal routing functionality into a single unified component. This consolidation reduces the number of separate design considerations and performance trade-offs that would otherwise be needed when accommodating decoupling technology in miniaturized packages, thereby reducing overall design complexity while enabling device miniaturization.
Data Source
AI summary
A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.