Stepped 3D Memory Contact Structure for Reliable Peripheral Links
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in improving operational reliability due to complex structures and potential defects in contact areas.
Innovation Solution
The semiconductor memory device incorporates a stack structure with alternately stacked insulating and conductive patterns, along with a peripheral contact structure that penetrates the stack structure and source layer, electrically connecting to the peripheral transistor. This design simplifies the connection structure and supports the stepped stack structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex contact structure is used to connect peripheral transistor to stack structure, then connection reliability may be improved, but device complexity and potential defects increase
Solution Approach 1:
The contact structure is divided into multiple segments: a first contact portion extending from the peripheral transistor, and a second contact portion extending from the stack structure. These segments are positioned at different heights and connected through a conductive pattern, allowing each segment to independently establish reliable connections while reducing overall structural complexity and defect risks.
Solution Approach 2:
The contact structure utilizes vertical dimensionality by extending the first and second contact portions in different directions (first direction and second direction respectively) and positioning them at different heights. This three-dimensional arrangement simplifies the connection path while maintaining reliability, avoiding complex lateral routing.
2Device complexity
If a simple connection structure is used between peripheral transistor and conductive pattern, then device complexity is reduced, but connection reliability may deteriorate
Solution Approach 1:
The connection is segmented into multiple portions: the first contact portion from the peripheral transistor, the second contact portion from the stack structure, and the conductive pattern connecting them. This segmentation allows each component to be optimized independently, maintaining simple overall structure while ensuring reliable electrical connection through the conductive pattern.
Solution Approach 2:
The conductive pattern acts as an intermediary element that connects the first contact portion and the second contact portion. This intermediary allows the peripheral transistor and stack structure to be connected through a simple, reliable path without requiring complex direct integration, thereby maintaining both simplicity and reliability.
3Ease of manufacture
If the peripheral contact structure level is lower than the uppermost conductive pattern, then manufacturing is simplified, but electrical connection reliability deteriorates
Solution Approach 1:
The solution utilizes vertical positioning in the third direction to resolve the level difference between the peripheral contact structure and the uppermost conductive pattern. The first and second contact portions extend in different directions and are positioned at different heights, creating a three-dimensional connection path that maintains manufacturing simplicity while ensuring reliable electrical connection through proper vertical alignment.
Data Source
AI summary
A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.