Stepped 3D NAND Pillars for Stable Threshold Voltage
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Solution Overview
Problem
Conventional 3D NAND electronic devices face challenges in designing and fabricating pillars with desired electrical performance due to damage from sacrificial material removal and dopant diffusion, leading to pinholes and low initial threshold voltage, which affects memory cell programming.
Innovation Solution
The electronic device features pillars with channel materials of different thicknesses in the cell and lateral contact regions, where the channel material is thinner in the cell region and thicker in the lateral contact region, with a stepped pillar structure to prevent dopant diffusion and protect cell films during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sacrificial material is removed to achieve lateral contact with channels, then lateral contact is established, but pinholes are formed in the channel material causing damage to cell films
Solution Approach 1:
A protective layer is formed over the channel material before sacrificial material removal. This protective layer prevents etchants from attacking the channel material during the sacrificial material removal process, thereby preventing pinhole formation while still allowing lateral contact to be established after the protective layer is selectively removed
2Ease of operation
If doped polysilicon material is used to replace sacrificial material for lateral contact, then lateral contact is achieved, but dopants diffuse through pinholes to the cell region causing low initial threshold voltage
Solution Approach 1:
The protective layer is formed beforehand to prevent pinhole formation during sacrificial material removal. By preventing pinholes from forming in the first place, dopant diffusion pathways are blocked, ensuring that dopants remain confined to the lateral contact region and do not contaminate the cell region, thus maintaining precise threshold voltage control
Solution Approach 2:
The protective layer acts as an intermediary barrier between the dopants in the doped polysilicon lateral contact material and the channel material in the cell region. This intermediary prevents direct dopant diffusion by providing a physical barrier, thereby maintaining the electrical characteristics of the memory cell
3Ease of manufacture
If uniform channel material thickness is used throughout the pillar, then fabrication is simplified, but electrical performance is compromised due to dopant diffusion and high contact resistance
Solution Approach 1:
The channel material is designed with different thicknesses in different regions: a first thickness in the cell region and a second (greater) thickness in the lateral contact region. This local quality variation allows the lateral contact region to have better electrical contact while the cell region maintains its electrical characteristics, thereby improving overall device performance without significantly complicating the fabrication process
Data Source
AI summary
An electronic device comprises memory pillars comprising a channel material. The memory pillars extend through both a cell region and a lateral contact region. A portion of the memory pillars in the lateral contact region comprise at least one first step and at least one second step. The electronic device comprises a source contact in direct contact with the channel material in the at least one second step of the portion of the memory pillars in the lateral contact region. Additional electronic devices and methods of forming an electronic device are also disclosed.