Stepped Multi-Stack Nanosheet Transistors for Direct Source/Drain Contacts
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Solution Overview
Problem
Current semiconductor devices, such as finFETs and nanosheet structures, face limitations in miniaturization and current flow due to small effective channel widths and current leakage, which restricts further performance enhancement.
Innovation Solution
A semiconductor device with a stepped nanosheet structure is introduced, featuring different channel region widths between nanosheet layers, allowing for a more efficient source/drain contact structure connection and reduced size through vertical stacking and isolation layers, enabling direct and straight connections without additional complexity or size increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet layers are vertically stacked to increase device density and effective channel width, then current flow capability is improved, but source/drain contact structure connection becomes complex and device size increases
Solution Approach 1:
The patent transitions from planar contact structures to three-dimensional stepped contact structures that vertically align with the nanosheet stacking arrangement. The contact structures extend through multiple levels to reach source/drain regions at different heights, enabling direct connections without lateral routing complexity.
Solution Approach 2:
The contact structures are nested within the vertical stack of nanosheet layers, with each contact structure positioned to align with its corresponding nanosheet level. This nesting approach allows multiple contact structures to share the same vertical footprint, reducing overall device area while maintaining individual access to each nanosheet layer.
2Ease of manufacture
If traditional planar transistor structures are used, then manufacturing process is simple, but effective channel width is limited and current flow is restricted
Solution Approach 1:
The invention extends the channel structure from two-dimensional planar geometry to three-dimensional vertical stacking. Multiple nanosheet layers are stacked vertically to create parallel current paths, effectively multiplying the total channel width while maintaining compatibility with scaled manufacturing processes.
Solution Approach 2:
The channel is segmented into multiple discrete nanosheet layers that can be independently formed and controlled. Each nanosheet layer acts as a separate current-carrying path, allowing the total effective channel width to be the sum of individual layer widths while enabling independent optimization of each layer's properties.
3Volume of moving object
If finFET structure with slim fin-shaped channel is used, then device miniaturization is achieved, but current leakage through bottom surface contacting substrate occurs
Solution Approach 1:
The channel structure transitions from a fin extending upward from the substrate to nanosheets suspended above the substrate. This vertical displacement separates the channel from the substrate, eliminating the leakage path while maintaining small device footprint through vertical stacking.
Solution Approach 2:
Dielectric materials are introduced as intermediary layers between the nanosheet channels and the substrate. These dielectric layers provide electrical isolation that prevents current leakage while allowing the nanosheets to be positioned at optimized heights for device performance.
Data Source
AI summary
A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.